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> > > =20 > > > }; > > >=20 > > > + dfll: clock@70110000 { > > > + compatible =3D "nvidia,tegra114-dfll"; > > > + reg =3D <0x70110000 0x100>, /* DFLL control */ > > > + <0x70110000 0x100>, /* I2C output control */ > > > + <0x70110100 0x100>, /* Integrated I2C controller = */ > > > + <0x70110200 0x100>; /* Look-up table RAM */ > > > + interrupts =3D ; > > > + clocks =3D <&tegra_car TEGRA114_CLK_DFLL_SOC>, > > > + <&tegra_car TEGRA114_CLK_DFLL_REF>, > > > + <&tegra_car TEGRA114_CLK_I2C5>; > > > + clock-names =3D "soc", "ref", "i2c"; > > > + resets =3D <&tegra_car TEGRA114_RST_DFLL_DVCO>; > > > + reset-names =3D "dvco"; > > > + #clock-cells =3D <0>; > > > + clock-output-names =3D "dfllCPU_out"; > > > + nvidia,sample-rate =3D <11500>; > >=20 > > Should this be 12500? That would match Tegra124 and a downstream kernel > > for > > Tegra114 I have. >=20 > I referred to tegratab and macallan boards in 3.4 kernel which give > 11500, maybe sample-rate was changed to 12500 later with tegra124 > addition? That's interesting. I was looking at the public roth (Shield Portable) kern= el,=20 which does not support Tegra124. I checked the L4T r17 release now, and it= =20 seems it's a newer version, where the sample rate has been changed to 11500= on=20 some boards due to a voltage undershoot issue with vdd_cpu on macallan/ tegratab [1]. So on macallan/tegratab, the vdd_cpu (smps123) ramp rate should be set to=20 2.5mV/us and sample-rate to 11500, while on other boards it can be 5mV/us w= ith=20 12500 for faster ramping. [1] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-2.6/+/ b92cab2d4cb6379aeded80adc4c5d0708c3f038e%5E%21/#F0 Cheers, Mikko >=20 > > > + nvidia,droop-ctrl =3D <0x00000f00>; > > > + nvidia,force-mode =3D <1>; > > > + nvidia,cf =3D <10>; > > > + nvidia,ci =3D <0>; > > > + nvidia,cg =3D <2>; > > > + status =3D "disabled"; > > > + }; > > > + > > >=20 > > > mmc@78000000 { > > > =20 > > > compatible =3D "nvidia,tegra114-sdhci"; > > > reg =3D <0x78000000 0x200>; > > >=20 > > > @@ -841,6 +866,15 @@ cpu@0 { > > >=20 > > > device_type =3D "cpu"; > > > compatible =3D "arm,cortex-a15"; > > > reg =3D <0>; > > >=20 > > > + > > > + clocks =3D <&tegra_car TEGRA114_CLK_CCLK_G>, > > > + <&tegra_car TEGRA114_CLK_CCLK_LP>, > > > + <&tegra_car TEGRA114_CLK_PLL_X>, > > > + <&tegra_car TEGRA114_CLK_PLL_P>, > > > + <&dfll>; > > > + clock-names =3D "cpu_g", "cpu_lp", "pll_x", "pl= l_p", > >=20 > > "dfll"; > >=20 > > > + /* FIXME: what's the actual transition time? */ > > > + clock-latency =3D <300000>; > > >=20 > > > }; > > > =20 > > > cpu@1 {