public inbox for linux-tegra@vger.kernel.org
 help / color / mirror / Atom feed
From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org,
	Stephen Warren <swarren@wwwdotorg.org>,
	linux-arm-kernel@lists.infradead.org,
	Jonathan Hunter <jonathanh@nvidia.com>
Subject: Re: [PATCH 1/2] arm64: tegra: Add pinmux for PWM-based DFLL support on Shield platform
Date: Tue, 2 Apr 2019 11:06:36 +0800	[thread overview]
Message-ID: <2c7c9268-0b95-fa49-294b-155a9499741e@nvidia.com> (raw)
In-Reply-To: <20190322095244.GF28640@ulmo>

On 3/22/19 5:52 PM, Thierry Reding wrote:
> On Fri, Mar 22, 2019 at 03:11:10PM +0800, Joseph Lo wrote:
>> Add pinmux for PWM-based DFLL support on Shield platform.
>>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> ---
>>   arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
> 
> There's been some discussion recently about moving away from programming
> pinmux in the kernel because it isn't always safe to do that. The idea
> is that early boot firmware (typically cboot) will already have set up
> the pinmux, so there's no need to do it again in the kernel.
> 
> These look like you're going to change this pin to/from tristate at
> runtime, so perhaps that's the kind of thing that we're okay with?
> 
> Adding Stephen for visibility.

Gentle ping.

Thanks,
Joseph

> 
> Thierry
> 
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
>> index 88a4b9333d84..c668f16c8574 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
>> @@ -1318,6 +1318,20 @@
>>   				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
>>   			};
>>   		};
>> +
>> +		dvfs_pwm_active_state: dvfs_pwm_active {
>> +			dvfs_pwm_pbb1 {
>> +				nvidia,pins = "dvfs_pwm_pbb1";
>> +				nvidia,tristate = <TEGRA_PIN_DISABLE>;
>> +			};
>> +		};
>> +
>> +		dvfs_pwm_inactive_state: dvfs_pwm_inactive {
>> +			dvfs_pwm_pbb1 {
>> +				nvidia,pins = "dvfs_pwm_pbb1";
>> +				nvidia,tristate = <TEGRA_PIN_ENABLE>;
>> +			};
>> +		};
>>   	};
>>   
>>   	serial@70006000 {
>> -- 
>> 2.21.0
>>

  reply	other threads:[~2019-04-02  3:06 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-22  7:11 [PATCH 1/2] arm64: tegra: Add pinmux for PWM-based DFLL support on Shield platform Joseph Lo
2019-03-22  7:11 ` [PATCH 2/2] arm64: tegra: Enable DFLL clock " Joseph Lo
2019-03-22  9:52 ` [PATCH 1/2] arm64: tegra: Add pinmux for PWM-based DFLL support " Thierry Reding
2019-04-02  3:06   ` Joseph Lo [this message]
2019-04-15  1:27     ` Joseph Lo

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=2c7c9268-0b95-fa49-294b-155a9499741e@nvidia.com \
    --to=josephl@nvidia.com \
    --cc=jonathanh@nvidia.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=swarren@wwwdotorg.org \
    --cc=thierry.reding@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox