Re: [PATCH v7 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

On 05/03/26 4:28 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:27:50PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> Currently, the default setting is that CLKREQ# signal of a Root Port
>> is internally overridden to '0' to enable REFCLK to flow out to the slot.
>> It is observed that one of the PCIe switches (case in point Broadcom PCIe
>> Gen4 switch) is propagating the CLKREQ# signal of the Root Port to the
>> downstream side of the switch and expecting the Endpoint devices to pull
>> it low so that it (PCIe switch) can give out the REFCLK although the Switch
>> as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this
>> patch drives the CLKREQ# of the Root Port itself low to avoid link up
>> issues between PCIe switch downstream port and Endpoint devices. This is
> 
> Is the CLKREQ# signal shared with the switch and the endpoint devices
> connected to its downstream port also?
> 
Yes, this is the observation.

>> not a wrong thing to do after all the CLKREQ# is anyway being overridden
>> to '0' internally and now it is just that the same is being propagated
>> outside also.
>>
> 
> What do you mean by 'propagating outside'?
> 
> And what is the difference between APPL_PINMUX_CLKREQ_OVERRIDE and
> APPL_PINMUX_CLKREQ_DEFAULT_VALUE?
> 
> - Mani
APPL_PINMUX_CLKREQ_OVERRIDE: This overrides CLKREQ# input PAD to PCIe 
controller.
APPL_PINMUX_CLKREQ_OVERRIDE: This overrides CLKREQ# output PAD to low.
Propagating outside means driving CLKREQ# pin as low.

- Manikanta

> 
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V6 -> V7: Fix commit message
>> Changes V1 -> V6: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index b1ae46761915..2f1f882fc737 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -44,6 +44,7 @@
>>   #define APPL_PINMUX_CLKREQ_OVERRIDE		BIT(3)
>>   #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN	BIT(4)
>>   #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE	BIT(5)
>> +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE	BIT(13)
>>   
>>   #define APPL_CTRL				0x4
>>   #define APPL_CTRL_SYS_PRE_DET_STATE		BIT(6)
>> @@ -1411,6 +1412,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>>   		val = appl_readl(pcie, APPL_PINMUX);
>>   		val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
>>   		val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
>> +		val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE;
>>   		appl_writel(pcie, val, APPL_PINMUX);
>>   	}
>>   
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic