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So, the issue described in this commit message is not applicable. This patch is disabling BAR2 and BAR4, after enumeration I see only BAR0. I think we should revert this patch. Please share your inputs on this. Thanks, Manikanta On 22/09/25 7:38 pm, Niklas Cassel wrote: > Tegra already defines all BARs expect for BAR0 as BAR_RESERVED. > This is sufficient for pci-epf-test to not allocate backing memory and to > not call set_bar() for those BARs. However, marking a BAR as BAR_RESERVED > does not mean that the BAR get disabled. > > The host side driver, pci_endpoint_test, simply does an ioremap for all > enabled BARs, and will run tests against all enabled BARs. (I.e. it will > run tests also against the BARs marked as BAR_RESERVED.) > > After running the BARs tests (which will write to all enabled BARs), the > inbound address translation is broken. > This is because the tegra controller exposes the ATU Port Logic Structure > in BAR4. So when BAR4 is written, the inbound address translation settings > get overwritten. > > To avoid this, implement the dw_pcie_ep_ops .init() callback and start off > by disabling all BARs (pci-epf-test will later enable/configure BARs that > are not defined as BAR_RESERVED). > > This matches the behavior of other PCIe endpoint drivers: > dra7xx, imx6, layerscape-ep, artpec6, dw-rockchip, qcom-ep, rcar-gen4, and > uniphier-ep. > > With this, the PCI endpoint kselftest test case CONSECUTIVE_BAR_TEST > (which was specifically made to detect address translation issues) passes. > > Cc: stable@vger.kernel.org > Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") > Signed-off-by: Niklas Cassel > --- > drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index 63d310e5335f4..7eb48cc13648e 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -1955,6 +1955,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg) > return IRQ_HANDLED; > } > > +static void tegra_pcie_ep_init(struct dw_pcie_ep *ep) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + enum pci_barno bar; > + > + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) > + dw_pcie_ep_reset_bar(pci, bar); > +}; > + > static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq) > { > /* Tegra194 supports only INTA */ > @@ -2030,6 +2039,7 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep) > } > > static const struct dw_pcie_ep_ops pcie_ep_ops = { > + .init = tegra_pcie_ep_init, > .raise_irq = tegra_pcie_ep_raise_irq, > .get_features = tegra_pcie_ep_get_features, > };