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> + opp-shared; > + > + core_opp_900: opp-900000 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-level =3D <900000>; > + }; > + > + core_opp_950: opp-950000 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-level =3D <950000>; > + }; > + > + core_opp_1000: opp-1000000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-level =3D <1000000>; > + }; > + > + core_opp_1050: opp-1050000 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-level =3D <1050000>; > + }; > + > + core_opp_1100: opp-1100000 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-level =3D <1100000>; > + }; > + > + core_opp_1120: opp-1120000 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-level =3D <1120000>; > + }; > + > + core_opp_1150: opp-1150000 { > + opp-microvolt =3D <1150000 1150000 1390000>; > + opp-level =3D <1150000>; > + }; > + > + core_opp_1170: opp-1170000 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-level =3D <1170000>; > + }; > + > + core_opp_1200: opp-1200000 { > + opp-microvolt =3D <1200000 1200000 1390000>; > + opp-level =3D <1200000>; > + }; > + > + core_opp_1250: opp-1250000 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-level =3D <1250000>; > + }; > + > + core_opp_1300: opp-1300000 { > + opp-microvolt =3D <1300000 1300000 1390000>; > + opp-level =3D <1300000>; > + }; > + > + core_opp_1350: opp-1350000 { > + opp-microvolt =3D <1350000 1350000 1390000>; > + opp-level =3D <1350000>; > + }; > + > + core_opp_1390: opp-1390000 { > + opp-microvolt =3D <1390000 1390000 1390000>; > + opp-level =3D <1390000>; > + }; > + }; > + > emc_icc_dvfs_opp_table: opp-table-emc { > compatible =3D "operating-points-v2"; > =20 > @@ -8,36 +78,42 @@ opp-12750000-900 { > opp-microvolt =3D <900000 900000 1390000>; > opp-hz =3D /bits/ 64 <12750000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > }; > =20 > opp-20400000-900 { > opp-microvolt =3D <900000 900000 1390000>; > opp-hz =3D /bits/ 64 <20400000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > }; > =20 > opp-40800000-900 { > opp-microvolt =3D <900000 900000 1390000>; > opp-hz =3D /bits/ 64 <40800000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > }; > =20 > opp-68000000-900 { > opp-microvolt =3D <900000 900000 1390000>; > opp-hz =3D /bits/ 64 <68000000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > }; > =20 > opp-102000000-900 { > opp-microvolt =3D <900000 900000 1390000>; > opp-hz =3D /bits/ 64 <102000000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > }; > =20 > opp-204000000-900 { > opp-microvolt =3D <900000 900000 1390000>; > opp-hz =3D /bits/ 64 <204000000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > opp-suspend; > }; > =20 > @@ -45,12 +121,14 @@ opp-312000000-1000 { > opp-microvolt =3D <1000000 1000000 1390000>; > opp-hz =3D /bits/ 64 <312000000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1000>; > }; > =20 > opp-408000000-1000 { > opp-microvolt =3D <1000000 1000000 1390000>; > opp-hz =3D /bits/ 64 <408000000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1000>; > }; > =20 > /* > @@ -64,24 +142,28 @@ opp-528000000-1100 { > opp-microvolt =3D <1100000 1100000 1390000>; > opp-hz =3D /bits/ 64 <528000000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > }; > =20 > opp-624000000-1100 { > opp-microvolt =3D <1100000 1100000 1390000>; > opp-hz =3D /bits/ 64 <624000000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > }; > =20 > opp-792000000-1100 { > opp-microvolt =3D <1100000 1100000 1390000>; > opp-hz =3D /bits/ 64 <792000000>; > opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > }; > =20 > opp-900000000-1200 { > opp-microvolt =3D <1200000 1200000 1390000>; > opp-hz =3D /bits/ 64 <900000000>; > opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1200>; > }; > }; > =20 > @@ -161,4 +243,1197 @@ opp-900000000 { > opp-peak-kBps =3D <14400000>; > }; > }; > + > + vi_dvfs_opp_table: opp-table-vi { > + compatible =3D "operating-points-v2"; > + > + opp-114000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <114000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-216000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <216000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-240000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <240000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-312000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <312000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-372000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <372000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-408000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <408000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-408000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <408000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1120>; > + }; > + }; > + > + epp_dvfs_opp_table: opp-table-epp { > + compatible =3D "operating-points-v2"; > + > + opp-192000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <192000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-240000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <240000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-228000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <228000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-300000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <300000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-300000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <300000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-384000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <384000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-396000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <396000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-468000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <468000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-492000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <492000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-528000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <528000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-516000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <516000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-564000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <564000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-552000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <552000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1170>; > + }; > + > + opp-600000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <600000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1170>; > + }; > + > + opp-600000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <600000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1250>; > + }; > + > + opp-636000000-1200 { > + opp-microvolt =3D <1200000 1200000 1390000>; > + opp-hz =3D /bits/ 64 <636000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1200>; > + }; > + > + opp-672000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <672000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1250>; > + }; > + > + opp-828000000-1390 { > + opp-microvolt =3D <1390000 1390000 1390000>; > + opp-hz =3D /bits/ 64 <828000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1390>; > + }; > + }; > + > + gr2d_dvfs_opp_table: opp-table-gr2d { > + compatible =3D "operating-points-v2"; > + > + opp-192000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <192000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-240000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <240000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-228000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <228000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-300000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <300000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-300000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <300000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-384000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <384000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-396000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <396000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-468000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <468000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-492000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <492000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-528000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <528000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-516000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <516000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-564000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <564000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-552000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <552000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1170>; > + }; > + > + opp-600000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <600000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1170>; > + }; > + > + opp-600000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <600000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1250>; > + }; > + > + opp-636000000-1200 { > + opp-microvolt =3D <1200000 1200000 1390000>; > + opp-hz =3D /bits/ 64 <636000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1200>; > + }; > + > + opp-672000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <672000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1250>; > + }; > + > + opp-828000000-1390 { > + opp-microvolt =3D <1390000 1390000 1390000>; > + opp-hz =3D /bits/ 64 <828000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1390>; > + }; > + }; > + > + gr3d_dvfs_opp_table: opp-table-gr3d { > + compatible =3D "operating-points-v2"; > + > + opp-192000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <192000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-240000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <240000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-228000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <228000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-300000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <300000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-300000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <300000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-384000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <384000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-396000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <396000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-468000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <468000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-492000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <492000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-528000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <528000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-516000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <516000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-564000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <564000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-552000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <552000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1170>; > + }; > + > + opp-600000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <600000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1170>; > + }; > + > + opp-600000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <600000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1250>; > + }; > + > + opp-636000000-1200 { > + opp-microvolt =3D <1200000 1200000 1390000>; > + opp-hz =3D /bits/ 64 <636000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1200>; > + }; > + > + opp-672000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <672000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1250>; > + }; > + > + opp-828000000-1390 { > + opp-microvolt =3D <1390000 1390000 1390000>; > + opp-hz =3D /bits/ 64 <828000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1390>; > + }; > + }; > + > + msenc_dvfs_opp_table: opp-table-msenc { > + compatible =3D "operating-points-v2"; > + > + opp-144000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <144000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-182000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <182000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-204000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <204000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-240000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <240000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-252000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <252000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-312000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <312000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-324000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <324000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-384000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <384000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-408000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <408000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-432000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <432000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-456000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <456000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-480000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <480000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-480000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <480000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1170>; > + }; > + }; > + > + tsec_dvfs_opp_table: opp-table-tsec { > + compatible =3D "operating-points-v2"; > + > + opp-144000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <144000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-182000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <182000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-204000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <204000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-240000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <240000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-252000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <252000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-312000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <312000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-324000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <324000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-384000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <384000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-408000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <408000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-432000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <432000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-456000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <456000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-480000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <480000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-480000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <480000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1170>; > + }; > + }; > + > + vde_dvfs_opp_table: opp-table-vde { > + compatible =3D "operating-points-v2"; > + > + opp-144000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <144000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-182000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <182000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-204000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <204000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-240000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <240000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-252000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <252000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-312000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <312000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-324000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <324000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-384000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <384000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-408000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <408000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-432000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <432000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-456000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <456000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-480000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <480000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-480000000-1170 { > + opp-microvolt =3D <1170000 1170000 1390000>; > + opp-hz =3D /bits/ 64 <480000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1170>; > + }; > + }; > + > + host1x_dvfs_opp_table: opp-table-host1x { > + compatible =3D "operating-points-v2"; > + > + opp-144000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <144000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-180000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <180000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-188000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <188000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-228000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <228000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-240000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <240000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-276000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <276000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1000>; > + }; > + > + opp-276000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <276000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-324000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <324000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-336000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <336000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1050>; > + }; > + > + opp-336000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <336000000>; > + opp-supported-hw =3D <0x0001>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-372000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <372000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1100>; > + }; > + > + opp-384000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <384000000>; > + opp-supported-hw =3D <0x000E>; > + required-opps =3D <&core_opp_1120>; > + }; > + }; > + > + pll_m_dvfs_opp_table: opp-table-pllm { > + compatible =3D "operating-points-v2"; > + > + opp-800000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <800000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-1066000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <1066000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1000>; > + }; > + }; > + > + pll_c_dvfs_opp_table: opp-table-pllc { > + compatible =3D "operating-points-v2"; > + > + opp-800000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <800000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-1066000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <1066000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1000>; > + }; > + }; > + > + pll_c2_dvfs_opp_table: opp-table-pllc2 { > + compatible =3D "operating-points-v2"; > + > + opp-800000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <800000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-1066000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <1066000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1000>; > + }; > + }; > + > + pll_c3_dvfs_opp_table: opp-table-pllc3 { > + compatible =3D "operating-points-v2"; > + > + opp-800000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <800000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-1066000000-1000 { > + opp-microvolt =3D <1000000 1000000 1390000>; > + opp-hz =3D /bits/ 64 <1066000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1000>; > + }; > + }; > + > + sbc1_dvfs_opp_table: opp-table-sbc1 { > + compatible =3D "operating-points-v2"; > + > + opp-48000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <48000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-52000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <52000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > + }; > + }; > + > + sbc2_dvfs_opp_table: opp-table-sbc2 { > + compatible =3D "operating-points-v2"; > + > + opp-48000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <48000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-52000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <52000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > + }; > + }; > + > + sbc3_dvfs_opp_table: opp-table-sbc3 { > + compatible =3D "operating-points-v2"; > + > + opp-48000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <48000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-52000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <52000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > + }; > + }; > + > + sbc4_dvfs_opp_table: opp-table-sbc4 { > + compatible =3D "operating-points-v2"; > + > + opp-48000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <48000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-52000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <52000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > + }; > + }; > + > + sbc5_dvfs_opp_table: opp-table-sbc5 { > + compatible =3D "operating-points-v2"; > + > + opp-48000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <48000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-52000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <52000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > + }; > + }; > + > + sbc6_dvfs_opp_table: opp-table-sbc6 { > + compatible =3D "operating-points-v2"; > + > + opp-48000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <48000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-52000000-1100 { > + opp-microvolt =3D <1100000 1100000 1390000>; > + opp-hz =3D /bits/ 64 <52000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1100>; > + }; > + }; > + > + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { > + compatible =3D "operating-points-v2"; > + > + opp-81600000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <81600000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-156000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <156000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-204000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <204000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1250>; > + }; > + }; > + > + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { > + compatible =3D "operating-points-v2"; > + > + opp-81600000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <81600000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-156000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <156000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-204000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <204000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1250>; > + }; > + }; > + > + sdmmc4_dvfs_opp_table: opp-table-sdmmc4 { > + compatible =3D "operating-points-v2"; > + > + opp-81600000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <81600000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + > + opp-156000000-1120 { > + opp-microvolt =3D <1120000 1120000 1390000>; > + opp-hz =3D /bits/ 64 <156000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1120>; > + }; > + > + opp-200000000-1250 { > + opp-microvolt =3D <1250000 1250000 1390000>; > + opp-hz =3D /bits/ 64 <200000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1250>; > + }; > + }; > + > + hdmi_dvfs_opp_table: opp-table-hdmi { > + compatible =3D "operating-points-v2"; > + > + opp-148500000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <148500000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-297000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <297000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1050>; > + }; > + }; > + > + disp1_dvfs_opp_table: opp-table-disp1 { > + compatible =3D "operating-points-v2"; > + > + opp-166000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <166000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-297000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <297000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1050>; > + }; > + }; > + > + disp2_dvfs_opp_table: opp-table-disp2 { > + compatible =3D "operating-points-v2"; > + > + opp-166000000-900 { > + opp-microvolt =3D <900000 900000 1390000>; > + opp-hz =3D /bits/ 64 <166000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_900>; > + }; > + > + opp-297000000-1050 { > + opp-microvolt =3D <1050000 1050000 1390000>; > + opp-hz =3D /bits/ 64 <297000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_1050>; > + }; > + }; > + > + xusb_falcon_dvfs_opp_table: opp-table-xusb-falcon { > + compatible =3D "operating-points-v2"; > + > + opp-336000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <336000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + }; > + > + xusb_host_dvfs_opp_table: opp-table-xusb-host { > + compatible =3D "operating-points-v2"; > + > + opp-112000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <112000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + }; > + > + xusb_dev_dvfs_opp_table: opp-table-xusb-dev { > + compatible =3D "operating-points-v2"; > + > + opp-58300000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <58300000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + }; > + > + xusb_ss_dvfs_opp_table: opp-table-xusb-ss { > + compatible =3D "operating-points-v2"; > + > + opp-122400000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <122400000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + }; > + > + xusb_fs_dvfs_opp_table: opp-table-xusb-fs { > + compatible =3D "operating-points-v2"; > + > + opp-48000000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <48000000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + }; > + > + xusb_hs_dvfs_opp_table: opp-table-xusb-hs { > + compatible =3D "operating-points-v2"; > + > + opp-61200000-950 { > + opp-microvolt =3D <950000 950000 1390000>; > + opp-hz =3D /bits/ 64 <61200000>; > + opp-supported-hw =3D <0x000F>; > + required-opps =3D <&core_opp_950>; > + }; > + }; > + > + /* Add usbd, usb2 and usb3 opps if needed */ > }; > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/n= vidia/tegra114.dtsi > index f1af206f50ee..143aa45a9791 100644 > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi > @@ -58,6 +58,8 @@ vi@54080000 { > clocks =3D <&tegra_car TEGRA114_CLK_VI>; > resets =3D <&tegra_car 20>; > reset-names =3D "vi"; > + power-domains =3D <&pd_venc>; > + operating-points-v2 =3D <&vi_dvfs_opp_table>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_VI>; > =20 > @@ -71,6 +73,8 @@ epp@540c0000 { > clocks =3D <&tegra_car TEGRA114_CLK_EPP>; > resets =3D <&tegra_car TEGRA114_CLK_EPP>; > reset-names =3D "epp"; > + power-domains =3D <&pd_heg>; > + operating-points-v2 =3D <&epp_dvfs_opp_table>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_EPP>; > =20 > @@ -84,6 +88,7 @@ isp@54100000 { > clocks =3D <&tegra_car TEGRA114_CLK_ISP>; > resets =3D <&tegra_car TEGRA114_CLK_ISP>; > reset-names =3D "isp"; > + power-domains =3D <&pd_venc>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_ISP>; > =20 > @@ -97,6 +102,8 @@ gr2d@54140000 { > clocks =3D <&tegra_car TEGRA114_CLK_GR2D>; > resets =3D <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; > reset-names =3D "2d", "mc"; > + power-domains =3D <&pd_heg>; > + operating-points-v2 =3D <&gr2d_dvfs_opp_table>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_G2>; > }; > @@ -107,6 +114,8 @@ gr3d@54180000 { > clocks =3D <&tegra_car TEGRA114_CLK_GR3D>; > resets =3D <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; > reset-names =3D "3d", "mc"; > + power-domains =3D <&pd_3d>; > + operating-points-v2 =3D <&gr3d_dvfs_opp_table>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_NV>; > }; > @@ -120,6 +129,8 @@ dc@54200000 { > clock-names =3D "dc", "parent"; > resets =3D <&tegra_car 27>; > reset-names =3D "dc"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&disp1_dvfs_opp_table>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_DC>; > =20 > @@ -150,6 +161,8 @@ dc@54240000 { > clock-names =3D "dc", "parent"; > resets =3D <&tegra_car 26>; > reset-names =3D "dc"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&disp2_dvfs_opp_table>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_DCB>; > =20 > @@ -180,6 +193,8 @@ hdmi@54280000 { > clock-names =3D "hdmi", "parent"; > resets =3D <&tegra_car 51>; > reset-names =3D "hdmi"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&hdmi_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -193,6 +208,7 @@ dsia: dsi@54300000 { > resets =3D <&tegra_car 48>; > reset-names =3D "dsi"; > nvidia,mipi-calibrate =3D <&mipi 0x060>; /* DSIA & DSIB pads */ > + power-domains =3D <&pd_core>; > status =3D "disabled"; > =20 > #address-cells =3D <1>; > @@ -209,6 +225,7 @@ dsib: dsi@54400000 { > resets =3D <&tegra_car 82>; > reset-names =3D "dsi"; > nvidia,mipi-calibrate =3D <&mipi 0x180>; /* DSIC & DSID pads */ > + power-domains =3D <&pd_core>; > status =3D "disabled"; > =20 > #address-cells =3D <1>; > @@ -222,6 +239,8 @@ msenc@544c0000 { > clocks =3D <&tegra_car TEGRA114_CLK_MSENC>; > resets =3D <&tegra_car TEGRA114_CLK_MSENC>; > reset-names =3D "mpe"; > + power-domains =3D <&pd_mpe>; > + operating-points-v2 =3D <&msenc_dvfs_opp_table>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_MSENC>; > =20 > @@ -234,6 +253,8 @@ tsec@54500000 { > interrupts =3D ; > clocks =3D <&tegra_car TEGRA114_CLK_TSEC>; > resets =3D <&tegra_car TEGRA114_CLK_TSEC>; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&tsec_dvfs_opp_table>; > =20 > iommus =3D <&mc TEGRA_SWGROUP_TSEC>; > =20 > @@ -393,6 +414,8 @@ vde@6001a000 { > reset-names =3D "vde", "mc"; > resets =3D <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; > iommus =3D <&mc TEGRA_SWGROUP_VDE>; > + power-domains =3D <&pd_vde>; > + operating-points-v2 =3D <&vde_dvfs_opp_table>; > }; > =20 > apbmisc@70000800 { > @@ -470,6 +493,7 @@ pwm: pwm@7000a000 { > clocks =3D <&tegra_car TEGRA114_CLK_PWM>; > resets =3D <&tegra_car 17>; > reset-names =3D "pwm"; > + power-domains =3D <&pd_core>; > status =3D "disabled"; > }; > =20 > @@ -560,6 +584,8 @@ spi@7000d400 { > reset-names =3D "spi"; > dmas =3D <&apbdma 15>, <&apbdma 15>; > dma-names =3D "rx", "tx"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sbc1_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -575,6 +601,8 @@ spi@7000d600 { > reset-names =3D "spi"; > dmas =3D <&apbdma 16>, <&apbdma 16>; > dma-names =3D "rx", "tx"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sbc2_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -590,6 +618,8 @@ spi@7000d800 { > reset-names =3D "spi"; > dmas =3D <&apbdma 17>, <&apbdma 17>; > dma-names =3D "rx", "tx"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sbc3_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -605,6 +635,8 @@ spi@7000da00 { > reset-names =3D "spi"; > dmas =3D <&apbdma 18>, <&apbdma 18>; > dma-names =3D "rx", "tx"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sbc4_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -620,6 +652,8 @@ spi@7000dc00 { > reset-names =3D "spi"; > dmas =3D <&apbdma 27>, <&apbdma 27>; > dma-names =3D "rx", "tx"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sbc5_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -635,6 +669,8 @@ spi@7000de00 { > reset-names =3D "spi"; > dmas =3D <&apbdma 28>, <&apbdma 28>; > dma-names =3D "rx", "tx"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sbc6_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -661,6 +697,86 @@ tegra_pmc: pmc@7000e400 { > clocks =3D <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; > clock-names =3D "pclk", "clk32k_in"; > #clock-cells =3D <1>; > + > + pd_core: core-domain { > + #power-domain-cells =3D <0>; > + operating-points-v2 =3D <&core_opp_table>; > + }; > + > + powergates { > + /* > + * TODO: Add DIS and DISB domains once DC is able > + * to handle them properly. VENC and DISB should > + * set DIS as their source power domain due to > + * internal dependency. > + */ > + > + pd_heg: heg { > + clocks =3D <&tegra_car TEGRA114_CLK_GR2D>, > + <&tegra_car TEGRA114_CLK_EPP>; > + resets =3D <&mc TEGRA114_MC_RESET_2D>, > + <&mc TEGRA114_MC_RESET_EPP>, > + <&tegra_car TEGRA114_CLK_GR2D>, > + <&tegra_car TEGRA114_CLK_EPP>; > + power-domains =3D <&pd_core>; > + #power-domain-cells =3D <0>; > + }; > + > + pd_mpe: mpe { > + clocks =3D <&tegra_car TEGRA114_CLK_MSENC>; > + resets =3D <&mc TEGRA114_MC_RESET_MPE>, > + <&tegra_car TEGRA114_CLK_MSENC>; > + power-domains =3D <&pd_core>; > + #power-domain-cells =3D <0>; > + }; > + > + pd_3d: td { > + clocks =3D <&tegra_car TEGRA114_CLK_GR3D>; > + resets =3D <&mc TEGRA114_MC_RESET_3D>, > + <&tegra_car TEGRA114_CLK_GR3D>; > + power-domains =3D <&pd_core>; > + #power-domain-cells =3D <0>; > + }; > + > + pd_vde: vdec { > + clocks =3D <&tegra_car TEGRA114_CLK_VDE>; > + resets =3D <&mc TEGRA114_MC_RESET_VDE>, > + <&tegra_car TEGRA114_CLK_VDE>; > + power-domains =3D <&pd_core>; > + #power-domain-cells =3D <0>; > + }; > + > + pd_venc: venc { > + clocks =3D <&tegra_car TEGRA114_CLK_ISP>, > + <&tegra_car TEGRA114_CLK_VI>, > + <&tegra_car TEGRA114_CLK_CSI>; > + resets =3D <&mc TEGRA114_MC_RESET_ISP>, > + <&mc TEGRA114_MC_RESET_VI>, > + <&tegra_car TEGRA114_CLK_ISP>, > + <&tegra_car 20 /* VI */>, > + <&tegra_car TEGRA114_CLK_CSI>; > + power-domains =3D <&pd_core>; > + #power-domain-cells =3D <0>; > + }; > + > + pd_xusbss: xusba { > + clocks =3D <&tegra_car TEGRA114_CLK_XUSB_SS>; > + resets =3D <&tegra_car TEGRA114_CLK_XUSB_SS>; > + #power-domain-cells =3D <0>; > + }; > + > + pd_xusbdev: xusbb { > + clocks =3D <&tegra_car TEGRA114_CLK_XUSB_DEV>; > + resets =3D <&tegra_car 95>; > + #power-domain-cells =3D <0>; > + }; > + > + pd_xusbhost: xusbc { > + clocks =3D <&tegra_car TEGRA114_CLK_XUSB_HOST>; > + resets =3D <&tegra_car TEGRA114_CLK_XUSB_HOST>; > + #power-domain-cells =3D <0>; > + }; > + }; > }; > =20 > fuse@7000f800 { > @@ -670,6 +786,7 @@ fuse@7000f800 { > clock-names =3D "fuse"; > resets =3D <&tegra_car 39>; > reset-names =3D "fuse"; > + power-domains =3D <&pd_core>; > }; > =20 > mc: memory-controller@70019000 { > @@ -691,6 +808,7 @@ emc: external-memory-controller@7001b000 { > interrupts =3D ; > clocks =3D <&tegra_car TEGRA114_CLK_EMC>; > clock-names =3D "emc"; > + power-domains =3D <&pd_core>; > =20 > nvidia,memory-controller =3D <&mc>; > operating-points-v2 =3D <&emc_icc_dvfs_opp_table>; > @@ -885,6 +1003,8 @@ mmc@78000000 { > clock-names =3D "sdhci"; > resets =3D <&tegra_car 14>; > reset-names =3D "sdhci"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sdmmc1_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -907,6 +1027,8 @@ mmc@78000400 { > clock-names =3D "sdhci"; > resets =3D <&tegra_car 69>; > reset-names =3D "sdhci"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sdmmc3_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -918,6 +1040,8 @@ mmc@78000600 { > clock-names =3D "sdhci"; > resets =3D <&tegra_car 15>; > reset-names =3D "sdhci"; > + power-domains =3D <&pd_core>; > + operating-points-v2 =3D <&sdmmc4_dvfs_opp_table>; > status =3D "disabled"; > }; > =20 > @@ -930,6 +1054,7 @@ usb@7d000000 { > resets =3D <&tegra_car 22>; > reset-names =3D "usb"; > nvidia,phy =3D <&phy1>; > + power-domains =3D <&pd_core>; > status =3D "disabled"; > }; > =20 > @@ -970,6 +1095,7 @@ usb@7d008000 { > resets =3D <&tegra_car 59>; > reset-names =3D "usb"; > nvidia,phy =3D <&phy3>; > + power-domains =3D <&pd_core>; > status =3D "disabled"; > }; > =20 > --=20 > 2.51.0 >=20 >=20 I compared these core rail opps to what the roth (SHIELD Portable, T40T) ke= rnel defines. The HW 0x1 (speedo 0) opps match process_id=3D0/speedo_id=3D0 perfectly exc= ept for msenc/vde/tsec where the curve ends at 408MHz at 1120mV. The roth k= ernel also specifies a process_id=3D1/speedo_id=3D0 with almost the same ta= bles as process_id=3D1/speedo_id=3D1. process_id=3D0/speedo_id=3D1 doesn't = exist. For HW 0x2 (speedo 1), when compared to process_id=3D1, the opps in the dev= ice tree are in some cases slightly conservative compared to what the roth = kernel sets.=20 So I think all of that should work (except maybe the msenc/vde/tsec curve e= xtensions?), but it might be that there is some further potential on T40T. = Hopefully these values are actually just a difference between T40X and T40T= . In any case, Reviewed-by: Mikko Perttunen