Re: [PATCH v6 12/13] PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on

[Vidya Sagar <vidyas@nvidia.com>]

On 24/02/26 00:11, Manikanta Maddireddy wrote:
> When PERST# is deasserted twice (assert -> deassert -> assert -> deassert),
> a CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc
> (PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify()
> and dw_pcie_ep_cleanup() are called before reset_control_deassert() powers
> on the controller core.
> 
> The call chain that causes the timeout:
>   pex_ep_event_pex_rst_deassert()
>     pci_epc_deinit_notify()
>       pci_epf_test_epc_deinit()
>         pci_epf_test_clear_bar()
>           pci_epc_clear_bar()
>             dw_pcie_ep_clear_bar()
>               __dw_pcie_ep_reset_bar()
>                 dw_pcie_dbi_ro_wr_en()  <- Accesses 0x8bc DBI register
>     reset_control_deassert(pcie->core_rst)  <- Core powered on HERE
> 
> The DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only
> accessible after the controller core is powered on via
> reset_control_deassert(pcie->core_rst). Accessing them before this point
> results in a CBB timeout because the hardware is not yet operational.
> 
> Fix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to
> after reset_control_deassert(pcie->core_rst), ensuring the controller is
> fully powered on before any DBI register accesses occur.
> 
> Fixes: 40e2125381dc ("PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()")
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index f107f2eb98fd..256a5d1eba16 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1729,10 +1729,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  		goto fail_phy;
>  	}
>  
> -	/* Perform cleanup that requires refclk */
> -	pci_epc_deinit_notify(pcie->pci.ep.epc);
> -	dw_pcie_ep_cleanup(&pcie->pci.ep);
> -
>  	/* Clear any stale interrupt statuses */
>  	appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
>  	appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
> @@ -1798,6 +1794,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  
>  	reset_control_deassert(pcie->core_rst);
>  
> +	/* Perform cleanup that requires refclk and core reset deasserted */
> +	pci_epc_deinit_notify(pcie->pci.ep.epc);
> +	dw_pcie_ep_cleanup(&pcie->pci.ep);
> +
>  	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
>  	val &= ~PORT_LOGIC_SPEED_CHANGE;
>  	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>