* [PATCH v4 00/10] Add support for tegra30 and cardhu
@ 2011-11-11 11:22 Peter De Schrijver
2011-11-11 11:22 ` [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 Peter De Schrijver
` (7 more replies)
0 siblings, 8 replies; 23+ messages in thread
From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Stephen Warren, linux-kernel, linux-tegra, Colin Cross,
Olof Johansson, Russell King, linux-arm-kernel
This patchset adds support for the tegra30 SoC and the cardhu development
board.
Pathset is on top of Will Deacon's ARM reset work.
Most important changes in v4:
* cleanup clock code to work on multiple tegra variants
* added dependencies to avoid building tegra20 only code for tegra30
Most important changes in v3:
* align with ARM restart rework. might need a bit of rework to merge with the
latest version of this.
* minor cleanups and reformats
Most important changes in v2:
* account for arch_reset cleanup
* seperate patch for renaming pinmux-t2.h and pinmux-t2-tables.c
* fixed bug in common cache initialization
* fixed compatibility with non DT boards (boottested on harmony)
* improved commit messages
Peter De Schrijver (10):
arm/tegra: initial device tree for tegra30
arm/tegra: cleanup tegra20 support
arm/tegra: prepare clock code for multiple tegra variants
arm/tegra: prepare early init for multiple tegra variants
arm/tegra: rename tegra20 pinmux files
arm/tegra: prepare pinmux code for multiple tegra variants
arm/tegra: add new fields to struct tegra_pingroup_desc
arm/tegra: pinmux tables and definitions for tegra30
arm/tegra: implement support for tegra30
arm/tegra: add support for tegra30 based board cardhu
arch/arm/boot/dts/tegra-cardhu.dts | 36 ++
arch/arm/boot/dts/tegra30.dtsi | 127 +++++++
arch/arm/mach-tegra/Kconfig | 33 ++-
arch/arm/mach-tegra/Makefile | 6 +-
arch/arm/mach-tegra/Makefile.boot | 1 +
arch/arm/mach-tegra/board-dt.c | 25 ++
arch/arm/mach-tegra/board-harmony-pcie.c | 1 +
arch/arm/mach-tegra/board-harmony-pinmux.c | 1 +
arch/arm/mach-tegra/board-harmony.c | 2 +-
arch/arm/mach-tegra/board-paz00-pinmux.c | 1 +
arch/arm/mach-tegra/board-paz00.c | 2 +-
arch/arm/mach-tegra/board-seaboard-pinmux.c | 2 +-
arch/arm/mach-tegra/board-seaboard.c | 6 +-
arch/arm/mach-tegra/board-trimslice-pinmux.c | 1 +
arch/arm/mach-tegra/board-trimslice.c | 2 +-
arch/arm/mach-tegra/board.h | 9 +-
arch/arm/mach-tegra/clock.c | 19 +-
arch/arm/mach-tegra/clock.h | 3 -
arch/arm/mach-tegra/common.c | 54 +++-
arch/arm/mach-tegra/include/mach/irqs.h | 2 -
arch/arm/mach-tegra/include/mach/pinmux-t2.h | 184 ----------
arch/arm/mach-tegra/include/mach/pinmux-tegra20.h | 184 ++++++++++
arch/arm/mach-tegra/include/mach/pinmux-tegra30.h | 320 ++++++++++++++++++
arch/arm/mach-tegra/include/mach/pinmux.h | 88 ++++-
arch/arm/mach-tegra/pinmux-t2-tables.c | 228 -------------
arch/arm/mach-tegra/pinmux-tegra20-tables.c | 244 +++++++++++++
arch/arm/mach-tegra/pinmux-tegra30-tables.c | 376 +++++++++++++++++++++
arch/arm/mach-tegra/pinmux.c | 157 ++++++---
arch/arm/mach-tegra/tegra2_clocks.c | 14 +-
arch/arm/mach-tegra/timer.c | 13 +-
30 files changed, 1603 insertions(+), 538 deletions(-)
create mode 100644 arch/arm/boot/dts/tegra-cardhu.dts
create mode 100644 arch/arm/boot/dts/tegra30.dtsi
delete mode 100644 arch/arm/mach-tegra/include/mach/pinmux-t2.h
create mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
create mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
delete mode 100644 arch/arm/mach-tegra/pinmux-t2-tables.c
create mode 100644 arch/arm/mach-tegra/pinmux-tegra20-tables.c
create mode 100644 arch/arm/mach-tegra/pinmux-tegra30-tables.c
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 2011-11-11 11:22 [PATCH v4 00/10] Add support for tegra30 and cardhu Peter De Schrijver @ 2011-11-11 11:22 ` Peter De Schrijver [not found] ` <1321010541-31337-2-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2011-11-11 11:22 ` [PATCH v4 02/10] arm/tegra: cleanup tegra20 support Peter De Schrijver ` (6 subsequent siblings) 7 siblings, 1 reply; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, Stephen Warren, linux-arm-kernel, linux-kernel, linux-tegra This patch adds the initial device tree for tegra30 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- arch/arm/boot/dts/tegra30.dtsi | 127 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 127 insertions(+), 0 deletions(-) create mode 100644 arch/arm/boot/dts/tegra30.dtsi diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi new file mode 100644 index 0000000..fabe243 --- /dev/null +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -0,0 +1,127 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra30"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@50041000 { + compatible = "nvidia,tegra30-gic", "nvidia,tegra20-gic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 70 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 116 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 124 >; + }; + + i2c@7000c700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = < 152 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x100>; + interrupts = < 85 >; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 64 65 66 67 87 119 121 >; + #gpio-cells = <2>; + gpio-controller; + }; + + serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 68 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 69 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 78 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 122 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 123 >; + }; + + sdhci@78000000 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000000 0x200>; + interrupts = < 46 >; + }; + + sdhci@78000200 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000200 0x200>; + interrupts = < 47 >; + }; + + sdhci@78000400 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000400 0x200>; + interrupts = < 51 >; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000600 0x200>; + interrupts = < 63 >; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra30-pinmux"; + reg = < 0x70000868 0xd0 /* Pad control registers */ + 0x70003000 0x3e0 >; /* Mux registers */ + }; +}; -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
[parent not found: <1321010541-31337-2-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 [not found] ` <1321010541-31337-2-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2011-11-12 3:26 ` Rob Herring [not found] ` <4EBDE766.5080505-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Rob Herring @ 2011-11-12 3:26 UTC (permalink / raw) To: Peter De Schrijver Cc: Stephen Warren, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On 11/11/2011 05:22 AM, Peter De Schrijver wrote: > This patch adds the initial device tree for tegra30 > > Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > arch/arm/boot/dts/tegra30.dtsi | 127 ++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 127 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/boot/dts/tegra30.dtsi > > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi > new file mode 100644 > index 0000000..fabe243 > --- /dev/null > +++ b/arch/arm/boot/dts/tegra30.dtsi > @@ -0,0 +1,127 @@ > +/include/ "skeleton.dtsi" > + > +/ { > + compatible = "nvidia,tegra30"; Needs documentation. > + interrupt-parent = <&intc>; > + > + intc: interrupt-controller@50041000 { > + compatible = "nvidia,tegra30-gic", "nvidia,tegra20-gic"; > + interrupt-controller; > + #interrupt-cells = <1>; Is the Tegra GIC really different from a standard A9 gic? You need to update to use the gic binding. The cells should be 3 for example. Rob > + reg = < 0x50041000 0x1000 >, > + < 0x50040100 0x0100 >; > + }; > + > + i2c@7000c000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; > + reg = <0x7000C000 0x100>; > + interrupts = < 70 >; > + }; > + > + i2c@7000c400 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; > + reg = <0x7000C400 0x100>; > + interrupts = < 116 >; > + }; > + > + i2c@7000c500 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; > + reg = <0x7000C500 0x100>; > + interrupts = < 124 >; > + }; > + > + i2c@7000c700 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; > + reg = <0x7000c700 0x100>; > + interrupts = < 152 >; > + }; > + > + i2c@7000d000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; > + reg = <0x7000D000 0x100>; > + interrupts = < 85 >; > + }; > + > + gpio: gpio@6000d000 { > + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; > + reg = < 0x6000d000 0x1000 >; > + interrupts = < 64 65 66 67 87 119 121 >; > + #gpio-cells = <2>; > + gpio-controller; > + }; > + > + serial@70006000 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006000 0x40>; > + reg-shift = <2>; > + interrupts = < 68 >; > + }; > + > + serial@70006040 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006040 0x40>; > + reg-shift = <2>; > + interrupts = < 69 >; > + }; > + > + serial@70006200 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006200 0x100>; > + reg-shift = <2>; > + interrupts = < 78 >; > + }; > + > + serial@70006300 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006300 0x100>; > + reg-shift = <2>; > + interrupts = < 122 >; > + }; > + > + serial@70006400 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006400 0x100>; > + reg-shift = <2>; > + interrupts = < 123 >; > + }; > + > + sdhci@78000000 { > + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; > + reg = <0x78000000 0x200>; > + interrupts = < 46 >; > + }; > + > + sdhci@78000200 { > + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; > + reg = <0x78000200 0x200>; > + interrupts = < 47 >; > + }; > + > + sdhci@78000400 { > + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; > + reg = <0x78000400 0x200>; > + interrupts = < 51 >; > + }; > + > + sdhci@78000600 { > + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; > + reg = <0x78000600 0x200>; > + interrupts = < 63 >; > + }; > + > + pinmux: pinmux@70000000 { > + compatible = "nvidia,tegra30-pinmux"; > + reg = < 0x70000868 0xd0 /* Pad control registers */ > + 0x70003000 0x3e0 >; /* Mux registers */ > + }; > +}; ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <4EBDE766.5080505-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 [not found] ` <4EBDE766.5080505-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2011-11-14 15:25 ` Peter De Schrijver [not found] ` <20111114152518.GJ19069-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Peter De Schrijver @ 2011-11-14 15:25 UTC (permalink / raw) To: Rob Herring Cc: Stephen Warren, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Sat, Nov 12, 2011 at 04:26:30AM +0100, Rob Herring wrote: > On 11/11/2011 05:22 AM, Peter De Schrijver wrote: > > This patch adds the initial device tree for tegra30 > > > > Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > --- > > arch/arm/boot/dts/tegra30.dtsi | 127 ++++++++++++++++++++++++++++++++++++++++ > > 1 files changed, 127 insertions(+), 0 deletions(-) > > create mode 100644 arch/arm/boot/dts/tegra30.dtsi > > > > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi > > new file mode 100644 > > index 0000000..fabe243 > > --- /dev/null > > +++ b/arch/arm/boot/dts/tegra30.dtsi > > @@ -0,0 +1,127 @@ > > +/include/ "skeleton.dtsi" > > + > > +/ { > > + compatible = "nvidia,tegra30"; > > Needs documentation. > > > + interrupt-parent = <&intc>; > > + > > + intc: interrupt-controller@50041000 { > > + compatible = "nvidia,tegra30-gic", "nvidia,tegra20-gic"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > Is the Tegra GIC really different from a standard A9 gic? You need to > update to use the gic binding. The cells should be 3 for example. It has an extra 'legacy' interrupt controller like tegra20 has. This is used when waking up the CPU from power off mode. Cheers, Peter. ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <20111114152518.GJ19069-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>]
* Re: [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 [not found] ` <20111114152518.GJ19069-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> @ 2011-11-14 15:41 ` Rob Herring [not found] ` <4EC13699.5030205-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Rob Herring @ 2011-11-14 15:41 UTC (permalink / raw) To: Peter De Schrijver Cc: Stephen Warren, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 11/14/2011 09:25 AM, Peter De Schrijver wrote: > On Sat, Nov 12, 2011 at 04:26:30AM +0100, Rob Herring wrote: >> On 11/11/2011 05:22 AM, Peter De Schrijver wrote: >>> This patch adds the initial device tree for tegra30 >>> >>> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >>> --- >>> arch/arm/boot/dts/tegra30.dtsi | 127 ++++++++++++++++++++++++++++++++++++++++ >>> 1 files changed, 127 insertions(+), 0 deletions(-) >>> create mode 100644 arch/arm/boot/dts/tegra30.dtsi >>> >>> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi >>> new file mode 100644 >>> index 0000000..fabe243 >>> --- /dev/null >>> +++ b/arch/arm/boot/dts/tegra30.dtsi >>> @@ -0,0 +1,127 @@ >>> +/include/ "skeleton.dtsi" >>> + >>> +/ { >>> + compatible = "nvidia,tegra30"; >> >> Needs documentation. >> >>> + interrupt-parent = <&intc>; >>> + >>> + intc: interrupt-controller@50041000 { >>> + compatible = "nvidia,tegra30-gic", "nvidia,tegra20-gic"; >>> + interrupt-controller; >>> + #interrupt-cells = <1>; >> >> Is the Tegra GIC really different from a standard A9 gic? You need to >> update to use the gic binding. The cells should be 3 for example. > > It has an extra 'legacy' interrupt controller like tegra20 has. This is used > when waking up the CPU from power off mode. Although that is probably not part of the GIC h/w (i.e. at a different address) and should be described in the dts separately. That doesn't change the GIC binding or the fact that you are using arch/arm/common/gic.c though. Whether you have a different compatible string or not is not really the issue. That can already be supported if necessary. The issue is you are not using the existing GIC binding as a starting point and that has implications on every node using a GIC interrupt. Rob ^ permalink raw reply [flat|nested] 23+ messages in thread
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* Re: [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 [not found] ` <4EC13699.5030205-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2011-11-14 16:06 ` Peter De Schrijver [not found] ` <20111114160633.GK19069-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Peter De Schrijver @ 2011-11-14 16:06 UTC (permalink / raw) To: Rob Herring Cc: Stephen Warren, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Mon, Nov 14, 2011 at 04:41:13PM +0100, Rob Herring wrote: > On 11/14/2011 09:25 AM, Peter De Schrijver wrote: > > On Sat, Nov 12, 2011 at 04:26:30AM +0100, Rob Herring wrote: > >> On 11/11/2011 05:22 AM, Peter De Schrijver wrote: > >>> This patch adds the initial device tree for tegra30 > >>> > >>> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > >>> --- > >>> arch/arm/boot/dts/tegra30.dtsi | 127 ++++++++++++++++++++++++++++++++++++++++ > >>> 1 files changed, 127 insertions(+), 0 deletions(-) > >>> create mode 100644 arch/arm/boot/dts/tegra30.dtsi > >>> > >>> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi > >>> new file mode 100644 > >>> index 0000000..fabe243 > >>> --- /dev/null > >>> +++ b/arch/arm/boot/dts/tegra30.dtsi > >>> @@ -0,0 +1,127 @@ > >>> +/include/ "skeleton.dtsi" > >>> + > >>> +/ { > >>> + compatible = "nvidia,tegra30"; > >> > >> Needs documentation. > >> > >>> + interrupt-parent = <&intc>; > >>> + > >>> + intc: interrupt-controller@50041000 { > >>> + compatible = "nvidia,tegra30-gic", "nvidia,tegra20-gic"; > >>> + interrupt-controller; > >>> + #interrupt-cells = <1>; > >> > >> Is the Tegra GIC really different from a standard A9 gic? You need to > >> update to use the gic binding. The cells should be 3 for example. > > > > It has an extra 'legacy' interrupt controller like tegra20 has. This is used > > when waking up the CPU from power off mode. > > Although that is probably not part of the GIC h/w (i.e. at a different > address) and should be described in the dts separately. That doesn't > change the GIC binding or the fact that you are using > arch/arm/common/gic.c though. Whether you have a different compatible > string or not is not really the issue. That can already be supported if > necessary. The issue is you are not using the existing GIC binding as a > starting point and that has implications on every node using a GIC > interrupt. > The GIC is the same as the one used on tegra20. So I copied the binding from tegra20.dtsi. Is that one wrong too then? Cheers, Peter. ^ permalink raw reply [flat|nested] 23+ messages in thread
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* RE: [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 [not found] ` <20111114160633.GK19069-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> @ 2011-11-14 16:20 ` Stephen Warren [not found] ` <74CDBE0F657A3D45AFBB94109FB122FF1740805A80-C7FfzLzN0UxDw2glCA4ptUEOCMrvLtNR@public.gmane.org> 0 siblings, 1 reply; 23+ messages in thread From: Stephen Warren @ 2011-11-14 16:20 UTC (permalink / raw) To: Peter De Schrijver, Rob Herring Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Peter De Schrijver wrote at Monday, November 14, 2011 9:07 AM: > On Mon, Nov 14, 2011 at 04:41:13PM +0100, Rob Herring wrote: > > On 11/14/2011 09:25 AM, Peter De Schrijver wrote: > > > On Sat, Nov 12, 2011 at 04:26:30AM +0100, Rob Herring wrote: > > >> On 11/11/2011 05:22 AM, Peter De Schrijver wrote: > > >>> This patch adds the initial device tree for tegra30 ... > > >>> + interrupt-parent = <&intc>; > > >>> + > > >>> + intc: interrupt-controller@50041000 { > > >>> + compatible = "nvidia,tegra30-gic", "nvidia,tegra20-gic"; > > >>> + interrupt-controller; > > >>> + #interrupt-cells = <1>; > > >> > > >> Is the Tegra GIC really different from a standard A9 gic? You need to > > >> update to use the gic binding. The cells should be 3 for example. > > > > > > It has an extra 'legacy' interrupt controller like tegra20 has. This is used > > > when waking up the CPU from power off mode. > > > > Although that is probably not part of the GIC h/w (i.e. at a different > > address) and should be described in the dts separately. That doesn't > > change the GIC binding or the fact that you are using > > arch/arm/common/gic.c though. Whether you have a different compatible > > string or not is not really the issue. That can already be supported if > > necessary. The issue is you are not using the existing GIC binding as a > > starting point and that has implications on every node using a GIC > > interrupt. > > > > The GIC is the same as the one used on tegra20. So I copied the binding from > tegra20.dtsi. Is that one wrong too then? The existing Tegra20 .dtsi file doesn't use the new GIC bindings yet either, which as Peter points out is where he copied the GIC node from. My suggestion is that we merge the Tegra30 .dtsi as shown above, and then do a single pass to convert both tegra20.dtsi and tegra30.dtsi over to the new GIC binding, to prevent blocking the merge of tegra30.dtsi on the GIC binding rework. Does that sound fair? -- nvpublic ^ permalink raw reply [flat|nested] 23+ messages in thread
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* Re: [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 [not found] ` <74CDBE0F657A3D45AFBB94109FB122FF1740805A80-C7FfzLzN0UxDw2glCA4ptUEOCMrvLtNR@public.gmane.org> @ 2011-11-14 16:49 ` Rob Herring 0 siblings, 0 replies; 23+ messages in thread From: Rob Herring @ 2011-11-14 16:49 UTC (permalink / raw) To: Stephen Warren Cc: Peter De Schrijver, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 11/14/2011 10:20 AM, Stephen Warren wrote: > Peter De Schrijver wrote at Monday, November 14, 2011 9:07 AM: >> On Mon, Nov 14, 2011 at 04:41:13PM +0100, Rob Herring wrote: >>> On 11/14/2011 09:25 AM, Peter De Schrijver wrote: >>>> On Sat, Nov 12, 2011 at 04:26:30AM +0100, Rob Herring wrote: >>>>> On 11/11/2011 05:22 AM, Peter De Schrijver wrote: >>>>>> This patch adds the initial device tree for tegra30 > ... >>>>>> + interrupt-parent = <&intc>; >>>>>> + >>>>>> + intc: interrupt-controller@50041000 { >>>>>> + compatible = "nvidia,tegra30-gic", "nvidia,tegra20-gic"; >>>>>> + interrupt-controller; >>>>>> + #interrupt-cells = <1>; >>>>> >>>>> Is the Tegra GIC really different from a standard A9 gic? You need to >>>>> update to use the gic binding. The cells should be 3 for example. >>>> >>>> It has an extra 'legacy' interrupt controller like tegra20 has. This is used >>>> when waking up the CPU from power off mode. >>> >>> Although that is probably not part of the GIC h/w (i.e. at a different >>> address) and should be described in the dts separately. That doesn't >>> change the GIC binding or the fact that you are using >>> arch/arm/common/gic.c though. Whether you have a different compatible >>> string or not is not really the issue. That can already be supported if >>> necessary. The issue is you are not using the existing GIC binding as a >>> starting point and that has implications on every node using a GIC >>> interrupt. >>> >> >> The GIC is the same as the one used on tegra20. So I copied the binding from >> tegra20.dtsi. Is that one wrong too then? > > The existing Tegra20 .dtsi file doesn't use the new GIC bindings yet > either, which as Peter points out is where he copied the GIC node from. > My suggestion is that we merge the Tegra30 .dtsi as shown above, and then > do a single pass to convert both tegra20.dtsi and tegra30.dtsi over to the > new GIC binding, to prevent blocking the merge of tegra30.dtsi on the GIC > binding rework. Does that sound fair? > If the change was complex to address then I would agree, but it's not. In fact, the code to enable GIC DT binding is shorter than the additional copy of a wrong/incomplete/unused binding. I think it is needless churn doing as you suggest. Rob ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v4 02/10] arm/tegra: cleanup tegra20 support 2011-11-11 11:22 [PATCH v4 00/10] Add support for tegra30 and cardhu Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 Peter De Schrijver @ 2011-11-11 11:22 ` Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 04/10] arm/tegra: prepare early init for multiple tegra variants Peter De Schrijver ` (5 subsequent siblings) 7 siblings, 0 replies; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, Stephen Warren, linux-arm-kernel, linux-kernel, linux-tegra * add a dependency to ARCH_TEGRA_2x_SOC in Kconfig to all tegra20 based boards and TEGRA_PCI * make powergating dependent on ARCH_TEGRA_2x_SOC * remove dependency on ARCH_TEGRA_2x_SOC for clock.c Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- arch/arm/mach-tegra/Kconfig | 8 ++++++++ arch/arm/mach-tegra/Makefile | 3 +-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 91aff7c..2b1d49b 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -21,18 +21,21 @@ endchoice config TEGRA_PCI bool "PCI Express support" + depends on ARCH_TEGRA_2x_SOC select PCI comment "Tegra board type" config MACH_HARMONY bool "Harmony board" + depends on ARCH_TEGRA_2x_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Harmony development platform config MACH_KAEN bool "Kaen board" + depends on ARCH_TEGRA_2x_SOC select MACH_SEABOARD select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help @@ -40,11 +43,13 @@ config MACH_KAEN config MACH_PAZ00 bool "Paz00 board" + depends on ARCH_TEGRA_2x_SOC help Support for the Toshiba AC100/Dynabook AZ netbook config MACH_SEABOARD bool "Seaboard board" + depends on ARCH_TEGRA_2x_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Seaboard development platform. It will @@ -59,18 +64,21 @@ config MACH_TEGRA_DT config MACH_TRIMSLICE bool "TrimSlice board" + depends on ARCH_TEGRA_2x_SOC select TEGRA_PCI help Support for CompuLab TrimSlice platform config MACH_WARIO bool "Wario board" + depends on ARCH_TEGRA_2x_SOC select MACH_SEABOARD help Support for the Wario version of Seaboard config MACH_VENTANA bool "Ventana board" + depends on ARCH_TEGRA_2x_SOC select MACH_TEGRA_DT help Support for the nVidia Ventana development platform diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 91a07e1..7dc1db3 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -5,9 +5,8 @@ obj-y += irq.o obj-y += clock.o obj-y += timer.o obj-y += pinmux.o -obj-y += powergate.o obj-y += fuse.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 04/10] arm/tegra: prepare early init for multiple tegra variants 2011-11-11 11:22 [PATCH v4 00/10] Add support for tegra30 and cardhu Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 02/10] arm/tegra: cleanup tegra20 support Peter De Schrijver @ 2011-11-11 11:22 ` Peter De Schrijver [not found] ` <1321010541-31337-5-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> [not found] ` <1321010541-31337-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> ` (4 subsequent siblings) 7 siblings, 1 reply; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Stephen Warren, linux-kernel, linux-tegra, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel This patch splits the early init code in a common and a tegra20 specific part. L2 cache initialization is generalized and discovers the cache associativity at runtime. Also use arm_pm_restart instead of arm_arch_reset and reset the the system using the PMC reset feature rather then the CAR system reset. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- arch/arm/mach-tegra/board-dt.c | 21 ++++++++++++++ arch/arm/mach-tegra/board-harmony.c | 2 +- arch/arm/mach-tegra/board-paz00.c | 2 +- arch/arm/mach-tegra/board-seaboard.c | 6 ++-- arch/arm/mach-tegra/board-trimslice.c | 2 +- arch/arm/mach-tegra/board.h | 6 ++-- arch/arm/mach-tegra/clock.c | 5 --- arch/arm/mach-tegra/common.c | 47 ++++++++++++++++++++++---------- 8 files changed, 62 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index d368f8d..15ee974 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -118,6 +118,27 @@ static void __init tegra_dt_init(void) of_platform_populate(NULL, tegra_dt_match_table, tegra20_auxdata_lookup, NULL); } +static struct { + const char *machine; + void (*init)(void); +} early_init[] __initdata = { +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + { "nvidia,tegra20", tegra20_init_early }, +#endif +}; + +static void __init tegra_init_early(void) +{ + + int i; + + for (i = 0; i < ARRAY_SIZE(early_init); i++) + if (of_machine_is_compatible(early_init[i].machine)) + return early_init[i].init(); + + pr_warn("Unknown platform detected\n"); +} + static const char * tegra_dt_board_compat[] = { "nvidia,harmony", "nvidia,seaboard", diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index f0bdc5e..c422aeb 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -185,7 +185,7 @@ MACHINE_START(HARMONY, "harmony") .atag_offset = 0x100, .fixup = tegra_harmony_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .timer = &tegra_timer, .init_machine = tegra_harmony_init, diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 602f8dd..6997a47 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -188,7 +188,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ") .atag_offset = 0x100, .fixup = tegra_paz00_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .timer = &tegra_timer, .init_machine = tegra_paz00_init, diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c index bf13ea3..5e42e08 100644 --- a/arch/arm/mach-tegra/board-seaboard.c +++ b/arch/arm/mach-tegra/board-seaboard.c @@ -282,7 +282,7 @@ static void __init tegra_wario_init(void) MACHINE_START(SEABOARD, "seaboard") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .timer = &tegra_timer, .init_machine = tegra_seaboard_init, @@ -291,7 +291,7 @@ MACHINE_END MACHINE_START(KAEN, "kaen") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .timer = &tegra_timer, .init_machine = tegra_kaen_init, @@ -300,7 +300,7 @@ MACHINE_END MACHINE_START(WARIO, "wario") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .timer = &tegra_timer, .init_machine = tegra_wario_init, diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c index e008c0e..7117e81 100644 --- a/arch/arm/mach-tegra/board-trimslice.c +++ b/arch/arm/mach-tegra/board-trimslice.c @@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice") .atag_offset = 0x100, .fixup = tegra_trimslice_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .timer = &tegra_timer, .init_machine = tegra_trimslice_init, diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 1d14df7..355f488 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -23,9 +23,9 @@ #include <linux/types.h> -void tegra_assert_system_reset(char mode, const char *cmd); - -void __init tegra_init_early(void); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +void __init tegra20_init_early(void); +#endif void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_init_clock(void); diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 47f6366..e8d214d 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -399,11 +399,6 @@ void tegra_periph_reset_assert(struct clk *c) } EXPORT_SYMBOL(tegra_periph_reset_assert); -void __init tegra_init_clock(void) -{ - tegra2_init_clocks(); -} - /* * The SDMMC controllers on tegra20 have extra bits in the clock source * register that adjust the delay between the clock and data to compenstate diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 03c2bd4..3ad1ca3 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-harmony.c + * arch/arm/mach-tegra/common.c * * Copyright (C) 2010 Google, Inc. * @@ -33,16 +33,16 @@ void tegra_assert_system_reset(char mode, const char *cmd) { - void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); + void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); u32 reg; - /* use *_related to avoid spinlock since caches are off */ reg = readl_relaxed(reset); - reg |= 0x04; + reg |= 0x10; writel_relaxed(reg, reset); } -static __initdata struct tegra_clk_init_table common_clk_init_table[] = { +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, { "pll_p", "clk_m", 216000000, true }, @@ -58,26 +58,43 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "cpu", NULL, 0, true }, { NULL, NULL, 0, 0}, }; +#endif -static void __init tegra_init_cache(void) +static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) { #ifdef CONFIG_CACHE_L2X0 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + u32 aux_ctrl, cache_type; + + writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL); - writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); + cache_type = readl(p + L2X0_CACHE_TYPE); + aux_ctrl = (cache_type & 0x700) << (17-8); + aux_ctrl |= 0x6C000001; - l2x0_init(p, 0x6C080001, 0x8200c3fe); + l2x0_init(p, aux_ctrl, 0x8200c3fe); #endif } -void __init tegra_init_early(void) +static void __init tegra_setup_system_reset(void) { - tegra_init_fuse(); - tegra_init_clock(); - tegra_clk_init_from_table(common_clk_init_table); - tegra_init_cache(); + arm_pm_restart = tegra_assert_system_reset; +} + +static void __init tegra_common_init(void) +{ + tegra_setup_system_reset(); +} - arm_arch_reset = tegra_assert_system_reset; +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +void __init tegra20_init_early(void) +{ + tegra_init_fuse(); + tegra2_init_clocks(); + tegra_clk_init_from_table(tegra20_clk_init_table); + tegra_init_cache(0x331, 0x441); + tegra_common_init(); } +#endif -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
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* Re: [PATCH v4 04/10] arm/tegra: prepare early init for multiple tegra variants [not found] ` <1321010541-31337-5-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2011-11-11 11:45 ` Jamie Iles 2011-11-11 21:54 ` Stephen Warren 2011-11-11 21:53 ` Stephen Warren 1 sibling, 1 reply; 23+ messages in thread From: Jamie Iles @ 2011-11-11 11:45 UTC (permalink / raw) To: Peter De Schrijver Cc: Stephen Warren, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Peter, On Fri, Nov 11, 2011 at 01:22:10PM +0200, Peter De Schrijver wrote: > This patch splits the early init code in a common and a tegra20 specific part. > L2 cache initialization is generalized and discovers the cache associativity > at runtime. Also use arm_pm_restart instead of arm_arch_reset and reset the > the system using the PMC reset feature rather then the CAR system reset. > > Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > arch/arm/mach-tegra/board-dt.c | 21 ++++++++++++++ > arch/arm/mach-tegra/board-harmony.c | 2 +- > arch/arm/mach-tegra/board-paz00.c | 2 +- > arch/arm/mach-tegra/board-seaboard.c | 6 ++-- > arch/arm/mach-tegra/board-trimslice.c | 2 +- > arch/arm/mach-tegra/board.h | 6 ++-- > arch/arm/mach-tegra/clock.c | 5 --- > arch/arm/mach-tegra/common.c | 47 ++++++++++++++++++++++---------- > 8 files changed, 62 insertions(+), 29 deletions(-) > > diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c > index d368f8d..15ee974 100644 > --- a/arch/arm/mach-tegra/board-dt.c > +++ b/arch/arm/mach-tegra/board-dt.c > @@ -118,6 +118,27 @@ static void __init tegra_dt_init(void) > of_platform_populate(NULL, tegra_dt_match_table, tegra20_auxdata_lookup, NULL); > } > > +static struct { > + const char *machine; > + void (*init)(void); > +} early_init[] __initdata = { > +#ifdef CONFIG_ARCH_TEGRA_2x_SOC > + { "nvidia,tegra20", tegra20_init_early }, > +#endif > +}; > + > +static void __init tegra_init_early(void) > +{ > + > + int i; > + > + for (i = 0; i < ARRAY_SIZE(early_init); i++) > + if (of_machine_is_compatible(early_init[i].machine)) > + return early_init[i].init(); > + > + pr_warn("Unknown platform detected\n"); > +} Wouldn't it be better just to have separate machine descs for tegra20 and tegra30 and have a different .init_early for each? I'm not sure that this extra indirection buys us much, especially if we had to repeat it for any of the other entries. Jamie ^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 04/10] arm/tegra: prepare early init for multiple tegra variants 2011-11-11 11:45 ` Jamie Iles @ 2011-11-11 21:54 ` Stephen Warren 0 siblings, 0 replies; 23+ messages in thread From: Stephen Warren @ 2011-11-11 21:54 UTC (permalink / raw) To: Jamie Iles, Peter De Schrijver Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Jamie Iles wrote at Friday, November 11, 2011 4:45 AM: > On Fri, Nov 11, 2011 at 01:22:10PM +0200, Peter De Schrijver wrote: > > This patch splits the early init code in a common and a tegra20 specific part. > > L2 cache initialization is generalized and discovers the cache associativity > > at runtime. Also use arm_pm_restart instead of arm_arch_reset and reset the > > the system using the PMC reset feature rather then the CAR system reset. ... > > diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c ... > > +static struct { > > + const char *machine; > > + void (*init)(void); > > +} early_init[] __initdata = { > > +#ifdef CONFIG_ARCH_TEGRA_2x_SOC > > + { "nvidia,tegra20", tegra20_init_early }, > > +#endif > > +}; > > + > > +static void __init tegra_init_early(void) > > +{ > > + > > + int i; > > + > > + for (i = 0; i < ARRAY_SIZE(early_init); i++) > > + if (of_machine_is_compatible(early_init[i].machine)) > > + return early_init[i].init(); > > + > > + pr_warn("Unknown platform detected\n"); > > +} > > Wouldn't it be better just to have separate machine descs for tegra20 > and tegra30 and have a different .init_early for each? I'm not sure > that this extra indirection buys us much, especially if we had to repeat > it for any of the other entries. Jamie, thanks for pointing that. I think that does sound a lot simpler. -- nvpublic ^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 04/10] arm/tegra: prepare early init for multiple tegra variants [not found] ` <1321010541-31337-5-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2011-11-11 11:45 ` Jamie Iles @ 2011-11-11 21:53 ` Stephen Warren 1 sibling, 0 replies; 23+ messages in thread From: Stephen Warren @ 2011-11-11 21:53 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Peter De Schrijver wrote at Friday, November 11, 2011 4:22 AM: > This patch splits the early init code in a common and a tegra20 specific part. > L2 cache initialization is generalized and discovers the cache associativity > at runtime. Also use arm_pm_restart instead of arm_arch_reset and reset the > the system using the PMC reset feature rather then the CAR system reset. > diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h > -void tegra_assert_system_reset(char mode, const char *cmd); Given you explicitly removed that from the header... > +++ b/arch/arm/mach-tegra/clock.c > void tegra_assert_system_reset(char mode, const char *cmd) Maybe you want to make it static in the .c file too? -- nvpublic ^ permalink raw reply [flat|nested] 23+ messages in thread
[parent not found: <1321010541-31337-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* [PATCH v4 03/10] arm/tegra: prepare clock code for multiple tegra variants [not found] ` <1321010541-31337-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2011-11-11 11:22 ` Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 05/10] arm/tegra: rename tegra20 pinmux files Peter De Schrijver ` (2 subsequent siblings) 3 siblings, 0 replies; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, Stephen Warren, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-tegra-u79uwXL29TY76Z2rM5mHXA Rework the tegra20 clock code to support multiple tegra variants : * remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This functionality should be in clock.c. * compile tegra_sdmmc_tap_delay only on tegra20 as this feature will not be available in future variants. * don't export clk_measure_input_freq as its functionality is also available using clk_get_rate(). Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- arch/arm/mach-tegra/clock.c | 14 +++++++++----- arch/arm/mach-tegra/clock.h | 3 --- arch/arm/mach-tegra/tegra2_clocks.c | 14 +------------- arch/arm/mach-tegra/timer.c | 12 ++++++++---- 4 files changed, 18 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index f8d41ff..47f6366 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -387,13 +387,15 @@ EXPORT_SYMBOL(tegra_clk_init_from_table); void tegra_periph_reset_deassert(struct clk *c) { - tegra2_periph_reset_deassert(c); + BUG_ON(!c->ops->reset); + c->ops->reset(c, false); } EXPORT_SYMBOL(tegra_periph_reset_deassert); void tegra_periph_reset_assert(struct clk *c) { - tegra2_periph_reset_assert(c); + BUG_ON(!c->ops->reset); + c->ops->reset(c, true); } EXPORT_SYMBOL(tegra_periph_reset_assert); @@ -403,10 +405,11 @@ void __init tegra_init_clock(void) } /* - * The SDMMC controllers have extra bits in the clock source register that - * adjust the delay between the clock and data to compenstate for delays - * on the PCB. + * The SDMMC controllers on tegra20 have extra bits in the clock source + * register that adjust the delay between the clock and data to compenstate + * for delays on the PCB. */ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC void tegra_sdmmc_tap_delay(struct clk *c, int delay) { unsigned long flags; @@ -415,6 +418,7 @@ void tegra_sdmmc_tap_delay(struct clk *c, int delay) tegra2_sdmmc_tap_delay(c, delay); spin_unlock_irqrestore(&c->spinlock, flags); } +#endif #ifdef CONFIG_DEBUG_FS diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 688316a..18df129 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -146,11 +146,8 @@ struct tegra_clk_init_table { }; void tegra2_init_clocks(void); -void tegra2_periph_reset_deassert(struct clk *c); -void tegra2_periph_reset_assert(struct clk *c); void clk_init(struct clk *clk); struct clk *tegra_get_clock_by_name(const char *name); -unsigned long clk_measure_input_freq(void); int clk_reparent(struct clk *c, struct clk *parent); void tegra_clk_init_from_table(struct tegra_clk_init_table *table); unsigned long clk_get_rate_locked(struct clk *c); diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 371869d..2ab18f6 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32]; #define pmc_readl(reg) \ __raw_readl(reg_pmc_base + (reg)) -unsigned long clk_measure_input_freq(void) +static unsigned long clk_measure_input_freq(void) { u32 clock_autodetect; clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); @@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = { .disable = tegra2_clk_m_disable, }; -void tegra2_periph_reset_assert(struct clk *c) -{ - BUG_ON(!c->ops->reset); - c->ops->reset(c, true); -} - -void tegra2_periph_reset_deassert(struct clk *c) -{ - BUG_ON(!c->ops->reset); - c->ops->reset(c, false); -} - /* super clock functions */ /* "super clocks" on tegra have two-stage muxes and a clock skipping * super divider. We will ignore the clock skipping divider, since we diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 2f1df47..6366654 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -182,14 +182,18 @@ static struct irqaction tegra_timer_irq = { static void __init tegra_init_timer(void) { struct clk *clk; - unsigned long rate = clk_measure_input_freq(); + unsigned long rate; int ret; clk = clk_get_sys("timer", NULL); - if (IS_ERR(clk)) - pr_warn("Unable to get timer clock\n"); - else + if (IS_ERR(clk)) { + pr_warn("Unable to get timer clock." + " Assuming 12Mhz input clock.\n"); + rate = 12000000; + } else { clk_enable(clk); + rate = clk_get_rate(clk); + } /* * rtc registers are used by read_persistent_clock, keep the rtc clock -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 05/10] arm/tegra: rename tegra20 pinmux files [not found] ` <1321010541-31337-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2011-11-11 11:22 ` [PATCH v4 03/10] arm/tegra: prepare clock code " Peter De Schrijver @ 2011-11-11 11:22 ` Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 08/10] arm/tegra: pinmux tables and definitions for tegra30 Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 10/10] arm/tegra: add support for tegra30 based board cardhu Peter De Schrijver 3 siblings, 0 replies; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, Stephen Warren, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-tegra-u79uwXL29TY76Z2rM5mHXA Rename pinmux-t2.h and pinmux-t2-tables.c to the new tegra naming. This file will be reworked somewhat in the next patch to support multiple tegra SoC types. Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/board-seaboard-pinmux.c | 2 +- arch/arm/mach-tegra/include/mach/pinmux-t2.h | 184 ----------------- arch/arm/mach-tegra/include/mach/pinmux-tegra20.h | 184 +++++++++++++++++ arch/arm/mach-tegra/include/mach/pinmux.h | 2 +- arch/arm/mach-tegra/pinmux-t2-tables.c | 228 -------------------- arch/arm/mach-tegra/pinmux-tegra20-tables.c | 229 +++++++++++++++++++++ 7 files changed, 416 insertions(+), 415 deletions(-) delete mode 100644 arch/arm/mach-tegra/include/mach/pinmux-t2.h create mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra20.h delete mode 100644 arch/arm/mach-tegra/pinmux-t2-tables.c create mode 100644 arch/arm/mach-tegra/pinmux-tegra20-tables.c diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 7dc1db3..7f22103 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -9,7 +9,7 @@ obj-y += fuse.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c index fbce31d..9f12a51 100644 --- a/arch/arm/mach-tegra/board-seaboard-pinmux.c +++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c @@ -18,7 +18,7 @@ #include <linux/gpio.h> #include <mach/pinmux.h> -#include <mach/pinmux-t2.h> +#include <mach/pinmux-tegra20.h> #include "gpio-names.h" #include "board-seaboard.h" diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-t2.h deleted file mode 100644 index 4c26263..0000000 --- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h - * - * Copyright (C) 2010 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_PINMUX_T2_H -#define __MACH_TEGRA_PINMUX_T2_H - -enum tegra_pingroup { - TEGRA_PINGROUP_ATA = 0, - TEGRA_PINGROUP_ATB, - TEGRA_PINGROUP_ATC, - TEGRA_PINGROUP_ATD, - TEGRA_PINGROUP_ATE, - TEGRA_PINGROUP_CDEV1, - TEGRA_PINGROUP_CDEV2, - TEGRA_PINGROUP_CRTP, - TEGRA_PINGROUP_CSUS, - TEGRA_PINGROUP_DAP1, - TEGRA_PINGROUP_DAP2, - TEGRA_PINGROUP_DAP3, - TEGRA_PINGROUP_DAP4, - TEGRA_PINGROUP_DDC, - TEGRA_PINGROUP_DTA, - TEGRA_PINGROUP_DTB, - TEGRA_PINGROUP_DTC, - TEGRA_PINGROUP_DTD, - TEGRA_PINGROUP_DTE, - TEGRA_PINGROUP_DTF, - TEGRA_PINGROUP_GMA, - TEGRA_PINGROUP_GMB, - TEGRA_PINGROUP_GMC, - TEGRA_PINGROUP_GMD, - TEGRA_PINGROUP_GME, - TEGRA_PINGROUP_GPU, - TEGRA_PINGROUP_GPU7, - TEGRA_PINGROUP_GPV, - TEGRA_PINGROUP_HDINT, - TEGRA_PINGROUP_I2CP, - TEGRA_PINGROUP_IRRX, - TEGRA_PINGROUP_IRTX, - TEGRA_PINGROUP_KBCA, - TEGRA_PINGROUP_KBCB, - TEGRA_PINGROUP_KBCC, - TEGRA_PINGROUP_KBCD, - TEGRA_PINGROUP_KBCE, - TEGRA_PINGROUP_KBCF, - TEGRA_PINGROUP_LCSN, - TEGRA_PINGROUP_LD0, - TEGRA_PINGROUP_LD1, - TEGRA_PINGROUP_LD10, - TEGRA_PINGROUP_LD11, - TEGRA_PINGROUP_LD12, - TEGRA_PINGROUP_LD13, - TEGRA_PINGROUP_LD14, - TEGRA_PINGROUP_LD15, - TEGRA_PINGROUP_LD16, - TEGRA_PINGROUP_LD17, - TEGRA_PINGROUP_LD2, - TEGRA_PINGROUP_LD3, - TEGRA_PINGROUP_LD4, - TEGRA_PINGROUP_LD5, - TEGRA_PINGROUP_LD6, - TEGRA_PINGROUP_LD7, - TEGRA_PINGROUP_LD8, - TEGRA_PINGROUP_LD9, - TEGRA_PINGROUP_LDC, - TEGRA_PINGROUP_LDI, - TEGRA_PINGROUP_LHP0, - TEGRA_PINGROUP_LHP1, - TEGRA_PINGROUP_LHP2, - TEGRA_PINGROUP_LHS, - TEGRA_PINGROUP_LM0, - TEGRA_PINGROUP_LM1, - TEGRA_PINGROUP_LPP, - TEGRA_PINGROUP_LPW0, - TEGRA_PINGROUP_LPW1, - TEGRA_PINGROUP_LPW2, - TEGRA_PINGROUP_LSC0, - TEGRA_PINGROUP_LSC1, - TEGRA_PINGROUP_LSCK, - TEGRA_PINGROUP_LSDA, - TEGRA_PINGROUP_LSDI, - TEGRA_PINGROUP_LSPI, - TEGRA_PINGROUP_LVP0, - TEGRA_PINGROUP_LVP1, - TEGRA_PINGROUP_LVS, - TEGRA_PINGROUP_OWC, - TEGRA_PINGROUP_PMC, - TEGRA_PINGROUP_PTA, - TEGRA_PINGROUP_RM, - TEGRA_PINGROUP_SDB, - TEGRA_PINGROUP_SDC, - TEGRA_PINGROUP_SDD, - TEGRA_PINGROUP_SDIO1, - TEGRA_PINGROUP_SLXA, - TEGRA_PINGROUP_SLXC, - TEGRA_PINGROUP_SLXD, - TEGRA_PINGROUP_SLXK, - TEGRA_PINGROUP_SPDI, - TEGRA_PINGROUP_SPDO, - TEGRA_PINGROUP_SPIA, - TEGRA_PINGROUP_SPIB, - TEGRA_PINGROUP_SPIC, - TEGRA_PINGROUP_SPID, - TEGRA_PINGROUP_SPIE, - TEGRA_PINGROUP_SPIF, - TEGRA_PINGROUP_SPIG, - TEGRA_PINGROUP_SPIH, - TEGRA_PINGROUP_UAA, - TEGRA_PINGROUP_UAB, - TEGRA_PINGROUP_UAC, - TEGRA_PINGROUP_UAD, - TEGRA_PINGROUP_UCA, - TEGRA_PINGROUP_UCB, - TEGRA_PINGROUP_UDA, - /* these pin groups only have pullup and pull down control */ - TEGRA_PINGROUP_CK32, - TEGRA_PINGROUP_DDRC, - TEGRA_PINGROUP_PMCA, - TEGRA_PINGROUP_PMCB, - TEGRA_PINGROUP_PMCC, - TEGRA_PINGROUP_PMCD, - TEGRA_PINGROUP_PMCE, - TEGRA_PINGROUP_XM2C, - TEGRA_PINGROUP_XM2D, - TEGRA_MAX_PINGROUP, -}; - -enum tegra_drive_pingroup { - TEGRA_DRIVE_PINGROUP_AO1 = 0, - TEGRA_DRIVE_PINGROUP_AO2, - TEGRA_DRIVE_PINGROUP_AT1, - TEGRA_DRIVE_PINGROUP_AT2, - TEGRA_DRIVE_PINGROUP_CDEV1, - TEGRA_DRIVE_PINGROUP_CDEV2, - TEGRA_DRIVE_PINGROUP_CSUS, - TEGRA_DRIVE_PINGROUP_DAP1, - TEGRA_DRIVE_PINGROUP_DAP2, - TEGRA_DRIVE_PINGROUP_DAP3, - TEGRA_DRIVE_PINGROUP_DAP4, - TEGRA_DRIVE_PINGROUP_DBG, - TEGRA_DRIVE_PINGROUP_LCD1, - TEGRA_DRIVE_PINGROUP_LCD2, - TEGRA_DRIVE_PINGROUP_SDMMC2, - TEGRA_DRIVE_PINGROUP_SDMMC3, - TEGRA_DRIVE_PINGROUP_SPI, - TEGRA_DRIVE_PINGROUP_UAA, - TEGRA_DRIVE_PINGROUP_UAB, - TEGRA_DRIVE_PINGROUP_UART2, - TEGRA_DRIVE_PINGROUP_UART3, - TEGRA_DRIVE_PINGROUP_VI1, - TEGRA_DRIVE_PINGROUP_VI2, - TEGRA_DRIVE_PINGROUP_XM2A, - TEGRA_DRIVE_PINGROUP_XM2C, - TEGRA_DRIVE_PINGROUP_XM2D, - TEGRA_DRIVE_PINGROUP_XM2CLK, - TEGRA_DRIVE_PINGROUP_MEMCOMP, - TEGRA_DRIVE_PINGROUP_SDIO1, - TEGRA_DRIVE_PINGROUP_CRT, - TEGRA_DRIVE_PINGROUP_DDC, - TEGRA_DRIVE_PINGROUP_GMA, - TEGRA_DRIVE_PINGROUP_GMB, - TEGRA_DRIVE_PINGROUP_GMC, - TEGRA_DRIVE_PINGROUP_GMD, - TEGRA_DRIVE_PINGROUP_GME, - TEGRA_DRIVE_PINGROUP_OWR, - TEGRA_DRIVE_PINGROUP_UAD, - TEGRA_MAX_DRIVE_PINGROUP, -}; - -#endif - diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h new file mode 100644 index 0000000..6a40c1d --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h @@ -0,0 +1,184 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H +#define __MACH_TEGRA_PINMUX_TEGRA20_H + +enum tegra_pingroup { + TEGRA_PINGROUP_ATA = 0, + TEGRA_PINGROUP_ATB, + TEGRA_PINGROUP_ATC, + TEGRA_PINGROUP_ATD, + TEGRA_PINGROUP_ATE, + TEGRA_PINGROUP_CDEV1, + TEGRA_PINGROUP_CDEV2, + TEGRA_PINGROUP_CRTP, + TEGRA_PINGROUP_CSUS, + TEGRA_PINGROUP_DAP1, + TEGRA_PINGROUP_DAP2, + TEGRA_PINGROUP_DAP3, + TEGRA_PINGROUP_DAP4, + TEGRA_PINGROUP_DDC, + TEGRA_PINGROUP_DTA, + TEGRA_PINGROUP_DTB, + TEGRA_PINGROUP_DTC, + TEGRA_PINGROUP_DTD, + TEGRA_PINGROUP_DTE, + TEGRA_PINGROUP_DTF, + TEGRA_PINGROUP_GMA, + TEGRA_PINGROUP_GMB, + TEGRA_PINGROUP_GMC, + TEGRA_PINGROUP_GMD, + TEGRA_PINGROUP_GME, + TEGRA_PINGROUP_GPU, + TEGRA_PINGROUP_GPU7, + TEGRA_PINGROUP_GPV, + TEGRA_PINGROUP_HDINT, + TEGRA_PINGROUP_I2CP, + TEGRA_PINGROUP_IRRX, + TEGRA_PINGROUP_IRTX, + TEGRA_PINGROUP_KBCA, + TEGRA_PINGROUP_KBCB, + TEGRA_PINGROUP_KBCC, + TEGRA_PINGROUP_KBCD, + TEGRA_PINGROUP_KBCE, + TEGRA_PINGROUP_KBCF, + TEGRA_PINGROUP_LCSN, + TEGRA_PINGROUP_LD0, + TEGRA_PINGROUP_LD1, + TEGRA_PINGROUP_LD10, + TEGRA_PINGROUP_LD11, + TEGRA_PINGROUP_LD12, + TEGRA_PINGROUP_LD13, + TEGRA_PINGROUP_LD14, + TEGRA_PINGROUP_LD15, + TEGRA_PINGROUP_LD16, + TEGRA_PINGROUP_LD17, + TEGRA_PINGROUP_LD2, + TEGRA_PINGROUP_LD3, + TEGRA_PINGROUP_LD4, + TEGRA_PINGROUP_LD5, + TEGRA_PINGROUP_LD6, + TEGRA_PINGROUP_LD7, + TEGRA_PINGROUP_LD8, + TEGRA_PINGROUP_LD9, + TEGRA_PINGROUP_LDC, + TEGRA_PINGROUP_LDI, + TEGRA_PINGROUP_LHP0, + TEGRA_PINGROUP_LHP1, + TEGRA_PINGROUP_LHP2, + TEGRA_PINGROUP_LHS, + TEGRA_PINGROUP_LM0, + TEGRA_PINGROUP_LM1, + TEGRA_PINGROUP_LPP, + TEGRA_PINGROUP_LPW0, + TEGRA_PINGROUP_LPW1, + TEGRA_PINGROUP_LPW2, + TEGRA_PINGROUP_LSC0, + TEGRA_PINGROUP_LSC1, + TEGRA_PINGROUP_LSCK, + TEGRA_PINGROUP_LSDA, + TEGRA_PINGROUP_LSDI, + TEGRA_PINGROUP_LSPI, + TEGRA_PINGROUP_LVP0, + TEGRA_PINGROUP_LVP1, + TEGRA_PINGROUP_LVS, + TEGRA_PINGROUP_OWC, + TEGRA_PINGROUP_PMC, + TEGRA_PINGROUP_PTA, + TEGRA_PINGROUP_RM, + TEGRA_PINGROUP_SDB, + TEGRA_PINGROUP_SDC, + TEGRA_PINGROUP_SDD, + TEGRA_PINGROUP_SDIO1, + TEGRA_PINGROUP_SLXA, + TEGRA_PINGROUP_SLXC, + TEGRA_PINGROUP_SLXD, + TEGRA_PINGROUP_SLXK, + TEGRA_PINGROUP_SPDI, + TEGRA_PINGROUP_SPDO, + TEGRA_PINGROUP_SPIA, + TEGRA_PINGROUP_SPIB, + TEGRA_PINGROUP_SPIC, + TEGRA_PINGROUP_SPID, + TEGRA_PINGROUP_SPIE, + TEGRA_PINGROUP_SPIF, + TEGRA_PINGROUP_SPIG, + TEGRA_PINGROUP_SPIH, + TEGRA_PINGROUP_UAA, + TEGRA_PINGROUP_UAB, + TEGRA_PINGROUP_UAC, + TEGRA_PINGROUP_UAD, + TEGRA_PINGROUP_UCA, + TEGRA_PINGROUP_UCB, + TEGRA_PINGROUP_UDA, + /* these pin groups only have pullup and pull down control */ + TEGRA_PINGROUP_CK32, + TEGRA_PINGROUP_DDRC, + TEGRA_PINGROUP_PMCA, + TEGRA_PINGROUP_PMCB, + TEGRA_PINGROUP_PMCC, + TEGRA_PINGROUP_PMCD, + TEGRA_PINGROUP_PMCE, + TEGRA_PINGROUP_XM2C, + TEGRA_PINGROUP_XM2D, + TEGRA_MAX_PINGROUP, +}; + +enum tegra_drive_pingroup { + TEGRA_DRIVE_PINGROUP_AO1 = 0, + TEGRA_DRIVE_PINGROUP_AO2, + TEGRA_DRIVE_PINGROUP_AT1, + TEGRA_DRIVE_PINGROUP_AT2, + TEGRA_DRIVE_PINGROUP_CDEV1, + TEGRA_DRIVE_PINGROUP_CDEV2, + TEGRA_DRIVE_PINGROUP_CSUS, + TEGRA_DRIVE_PINGROUP_DAP1, + TEGRA_DRIVE_PINGROUP_DAP2, + TEGRA_DRIVE_PINGROUP_DAP3, + TEGRA_DRIVE_PINGROUP_DAP4, + TEGRA_DRIVE_PINGROUP_DBG, + TEGRA_DRIVE_PINGROUP_LCD1, + TEGRA_DRIVE_PINGROUP_LCD2, + TEGRA_DRIVE_PINGROUP_SDMMC2, + TEGRA_DRIVE_PINGROUP_SDMMC3, + TEGRA_DRIVE_PINGROUP_SPI, + TEGRA_DRIVE_PINGROUP_UAA, + TEGRA_DRIVE_PINGROUP_UAB, + TEGRA_DRIVE_PINGROUP_UART2, + TEGRA_DRIVE_PINGROUP_UART3, + TEGRA_DRIVE_PINGROUP_VI1, + TEGRA_DRIVE_PINGROUP_VI2, + TEGRA_DRIVE_PINGROUP_XM2A, + TEGRA_DRIVE_PINGROUP_XM2C, + TEGRA_DRIVE_PINGROUP_XM2D, + TEGRA_DRIVE_PINGROUP_XM2CLK, + TEGRA_DRIVE_PINGROUP_MEMCOMP, + TEGRA_DRIVE_PINGROUP_SDIO1, + TEGRA_DRIVE_PINGROUP_CRT, + TEGRA_DRIVE_PINGROUP_DDC, + TEGRA_DRIVE_PINGROUP_GMA, + TEGRA_DRIVE_PINGROUP_GMB, + TEGRA_DRIVE_PINGROUP_GMC, + TEGRA_DRIVE_PINGROUP_GMD, + TEGRA_DRIVE_PINGROUP_GME, + TEGRA_DRIVE_PINGROUP_OWR, + TEGRA_DRIVE_PINGROUP_UAD, + TEGRA_MAX_DRIVE_PINGROUP, +}; + +#endif + diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index bb7dfdb..b93df9e 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -18,7 +18,7 @@ #define __MACH_TEGRA_PINMUX_H #if defined(CONFIG_ARCH_TEGRA_2x_SOC) -#include "pinmux-t2.h" +#include "pinmux-tegra20.h" #else #error "Undefined Tegra architecture" #endif diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c deleted file mode 100644 index a0dc2bc..0000000 --- a/arch/arm/mach-tegra/pinmux-t2-tables.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * linux/arch/arm/mach-tegra/pinmux-t2-tables.c - * - * Common pinmux configurations for Tegra 2 SoCs - * - * Copyright (C) 2010 NVIDIA Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/spinlock.h> -#include <linux/io.h> -#include <linux/init.h> -#include <linux/string.h> - -#include <mach/iomap.h> -#include <mach/pinmux.h> -#include <mach/suspend.h> - -#define TRISTATE_REG_A 0x14 -#define PIN_MUX_CTL_REG_A 0x80 -#define PULLUPDOWN_REG_A 0xa0 -#define PINGROUP_REG_A 0x868 - -#define DRIVE_PINGROUP(pg_name, r) \ - [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ - .name = #pg_name, \ - .reg_bank = 3, \ - .reg = ((r) - PINGROUP_REG_A) \ - } - -const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { - DRIVE_PINGROUP(AO1, 0x868), - DRIVE_PINGROUP(AO2, 0x86c), - DRIVE_PINGROUP(AT1, 0x870), - DRIVE_PINGROUP(AT2, 0x874), - DRIVE_PINGROUP(CDEV1, 0x878), - DRIVE_PINGROUP(CDEV2, 0x87c), - DRIVE_PINGROUP(CSUS, 0x880), - DRIVE_PINGROUP(DAP1, 0x884), - DRIVE_PINGROUP(DAP2, 0x888), - DRIVE_PINGROUP(DAP3, 0x88c), - DRIVE_PINGROUP(DAP4, 0x890), - DRIVE_PINGROUP(DBG, 0x894), - DRIVE_PINGROUP(LCD1, 0x898), - DRIVE_PINGROUP(LCD2, 0x89c), - DRIVE_PINGROUP(SDMMC2, 0x8a0), - DRIVE_PINGROUP(SDMMC3, 0x8a4), - DRIVE_PINGROUP(SPI, 0x8a8), - DRIVE_PINGROUP(UAA, 0x8ac), - DRIVE_PINGROUP(UAB, 0x8b0), - DRIVE_PINGROUP(UART2, 0x8b4), - DRIVE_PINGROUP(UART3, 0x8b8), - DRIVE_PINGROUP(VI1, 0x8bc), - DRIVE_PINGROUP(VI2, 0x8c0), - DRIVE_PINGROUP(XM2A, 0x8c4), - DRIVE_PINGROUP(XM2C, 0x8c8), - DRIVE_PINGROUP(XM2D, 0x8cc), - DRIVE_PINGROUP(XM2CLK, 0x8d0), - DRIVE_PINGROUP(MEMCOMP, 0x8d4), - DRIVE_PINGROUP(SDIO1, 0x8e0), - DRIVE_PINGROUP(CRT, 0x8ec), - DRIVE_PINGROUP(DDC, 0x8f0), - DRIVE_PINGROUP(GMA, 0x8f4), - DRIVE_PINGROUP(GMB, 0x8f8), - DRIVE_PINGROUP(GMC, 0x8fc), - DRIVE_PINGROUP(GMD, 0x900), - DRIVE_PINGROUP(GME, 0x904), - DRIVE_PINGROUP(OWR, 0x908), - DRIVE_PINGROUP(UAD, 0x90c), -}; - -#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \ - tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \ - [TEGRA_PINGROUP_ ## pg_name] = { \ - .name = #pg_name, \ - .vddio = TEGRA_VDDIO_ ## vdd, \ - .funcs = { \ - TEGRA_MUX_ ## f0, \ - TEGRA_MUX_ ## f1, \ - TEGRA_MUX_ ## f2, \ - TEGRA_MUX_ ## f3, \ - }, \ - .func_safe = TEGRA_MUX_ ## f_safe, \ - .tri_bank = 0, \ - .tri_reg = ((tri_r) - TRISTATE_REG_A), \ - .tri_bit = tri_b, \ - .mux_bank = 1, \ - .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \ - .mux_bit = mux_b, \ - .pupd_bank = 2, \ - .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ - .pupd_bit = pupd_b, \ - } - -const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { - PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), - PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), - PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), - PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6), - PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8), - PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0), - PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2), - PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24), - PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24), - PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10), - PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12), - PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14), - PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16), - PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28), - PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18), - PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20), - PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22), - PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24), - PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26), - PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28), - PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20), - PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22), - PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24), - PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26), - PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24), - PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20), - PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6), - PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30), - PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22), - PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2), - PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22), - PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20), - PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8), - PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10), - PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12), - PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14), - PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2), - PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0), - PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20), - PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12), - PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12), - PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12), - PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12), - PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12), - PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12), - PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12), - PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12), - PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12), - PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12), - PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12), - PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12), - PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12), - PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12), - PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12), - PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12), - PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12), - PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12), - PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20), - PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18), - PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16), - PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14), - PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14), - PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22), - PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22), - PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22), - PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18), - PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20), - PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20), - PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20), - PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22), - PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20), - PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20), - PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20), - PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20), - PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22), - PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22), - PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16), - PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22), - PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30), - PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1), - PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4), - PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0), - PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1), - PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28), - PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30), - PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18), - PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22), - PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26), - PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28), - PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30), - PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16), - PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18), - PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4), - PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6), - PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8), - PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10), - PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12), - PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14), - PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16), - PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18), - PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0), - PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2), - PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4), - PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6), - PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8), - PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10), - PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16), - /* these pin groups only have pullup and pull down control */ - PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14), - PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26), - PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4), - PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6), - PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8), - PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10), - PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12), - PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), - PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), -}; diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c new file mode 100644 index 0000000..88642a5 --- /dev/null +++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -0,0 +1,229 @@ +/* + * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c + * + * Common pinmux configurations for Tegra20 SoCs + * + * Copyright (C) 2010 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/string.h> + +#include <mach/iomap.h> +#include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> +#include <mach/suspend.h> + +#define TRISTATE_REG_A 0x14 +#define PIN_MUX_CTL_REG_A 0x80 +#define PULLUPDOWN_REG_A 0xa0 +#define PINGROUP_REG_A 0x868 + +#define DRIVE_PINGROUP(pg_name, r) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg_bank = 3, \ + .reg = ((r) - PINGROUP_REG_A) \ + } + +const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { + DRIVE_PINGROUP(AO1, 0x868), + DRIVE_PINGROUP(AO2, 0x86c), + DRIVE_PINGROUP(AT1, 0x870), + DRIVE_PINGROUP(AT2, 0x874), + DRIVE_PINGROUP(CDEV1, 0x878), + DRIVE_PINGROUP(CDEV2, 0x87c), + DRIVE_PINGROUP(CSUS, 0x880), + DRIVE_PINGROUP(DAP1, 0x884), + DRIVE_PINGROUP(DAP2, 0x888), + DRIVE_PINGROUP(DAP3, 0x88c), + DRIVE_PINGROUP(DAP4, 0x890), + DRIVE_PINGROUP(DBG, 0x894), + DRIVE_PINGROUP(LCD1, 0x898), + DRIVE_PINGROUP(LCD2, 0x89c), + DRIVE_PINGROUP(SDMMC2, 0x8a0), + DRIVE_PINGROUP(SDMMC3, 0x8a4), + DRIVE_PINGROUP(SPI, 0x8a8), + DRIVE_PINGROUP(UAA, 0x8ac), + DRIVE_PINGROUP(UAB, 0x8b0), + DRIVE_PINGROUP(UART2, 0x8b4), + DRIVE_PINGROUP(UART3, 0x8b8), + DRIVE_PINGROUP(VI1, 0x8bc), + DRIVE_PINGROUP(VI2, 0x8c0), + DRIVE_PINGROUP(XM2A, 0x8c4), + DRIVE_PINGROUP(XM2C, 0x8c8), + DRIVE_PINGROUP(XM2D, 0x8cc), + DRIVE_PINGROUP(XM2CLK, 0x8d0), + DRIVE_PINGROUP(MEMCOMP, 0x8d4), + DRIVE_PINGROUP(SDIO1, 0x8e0), + DRIVE_PINGROUP(CRT, 0x8ec), + DRIVE_PINGROUP(DDC, 0x8f0), + DRIVE_PINGROUP(GMA, 0x8f4), + DRIVE_PINGROUP(GMB, 0x8f8), + DRIVE_PINGROUP(GMC, 0x8fc), + DRIVE_PINGROUP(GMD, 0x900), + DRIVE_PINGROUP(GME, 0x904), + DRIVE_PINGROUP(OWR, 0x908), + DRIVE_PINGROUP(UAD, 0x90c), +}; + +#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \ + tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \ + [TEGRA_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .vddio = TEGRA_VDDIO_ ## vdd, \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_ ## f2, \ + TEGRA_MUX_ ## f3, \ + }, \ + .func_safe = TEGRA_MUX_ ## f_safe, \ + .tri_bank = 0, \ + .tri_reg = ((tri_r) - TRISTATE_REG_A), \ + .tri_bit = tri_b, \ + .mux_bank = 1, \ + .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \ + .mux_bit = mux_b, \ + .pupd_bank = 2, \ + .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ + .pupd_bit = pupd_b, \ + } + +const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { + PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), + PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), + PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), + PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6), + PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8), + PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0), + PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2), + PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24), + PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24), + PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10), + PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12), + PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14), + PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16), + PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28), + PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18), + PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20), + PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22), + PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24), + PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26), + PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28), + PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20), + PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22), + PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24), + PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26), + PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24), + PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20), + PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6), + PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30), + PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22), + PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2), + PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22), + PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20), + PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8), + PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10), + PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12), + PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14), + PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2), + PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0), + PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20), + PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12), + PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12), + PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12), + PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12), + PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12), + PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12), + PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12), + PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12), + PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12), + PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12), + PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12), + PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12), + PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12), + PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12), + PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12), + PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12), + PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12), + PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12), + PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20), + PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18), + PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16), + PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14), + PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14), + PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22), + PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22), + PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22), + PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18), + PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20), + PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20), + PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20), + PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22), + PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20), + PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20), + PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20), + PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20), + PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22), + PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22), + PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16), + PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22), + PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30), + PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1), + PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4), + PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0), + PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1), + PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28), + PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30), + PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18), + PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22), + PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26), + PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28), + PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30), + PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16), + PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18), + PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4), + PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6), + PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8), + PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10), + PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12), + PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14), + PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16), + PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18), + PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0), + PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2), + PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4), + PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6), + PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8), + PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10), + PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16), + /* these pin groups only have pullup and pull down control */ + PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14), + PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26), + PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4), + PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6), + PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8), + PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10), + PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12), + PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), + PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), +}; -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 08/10] arm/tegra: pinmux tables and definitions for tegra30 [not found] ` <1321010541-31337-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2011-11-11 11:22 ` [PATCH v4 03/10] arm/tegra: prepare clock code " Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 05/10] arm/tegra: rename tegra20 pinmux files Peter De Schrijver @ 2011-11-11 11:22 ` Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 10/10] arm/tegra: add support for tegra30 based board cardhu Peter De Schrijver 3 siblings, 0 replies; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, Stephen Warren, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-tegra-u79uwXL29TY76Z2rM5mHXA Define the pinmuxing and pindrive tables for tegra30. The pinmux table defines the available functions for each pinmux group. The pindrive table defines the default pullup or pulldowns for each group. Derived from code by Scott Williams (scwilliams-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org) Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/include/mach/pinmux-tegra30.h | 320 ++++++++++++++++++ arch/arm/mach-tegra/include/mach/pinmux.h | 53 +++ arch/arm/mach-tegra/pinmux-tegra30-tables.c | 376 +++++++++++++++++++++ arch/arm/mach-tegra/pinmux.c | 48 +++ 5 files changed, 798 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra30.h create mode 100644 arch/arm/mach-tegra/pinmux-tegra30-tables.c diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 7f22103..a5071f3 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h new file mode 100644 index 0000000..c1aee3e --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h @@ -0,0 +1,320 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h + * + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010,2011 Nvidia, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H +#define __MACH_TEGRA_PINMUX_TEGRA30_H + +enum tegra_pingroup { + TEGRA_PINGROUP_ULPI_DATA0 = 0, + TEGRA_PINGROUP_ULPI_DATA1, + TEGRA_PINGROUP_ULPI_DATA2, + TEGRA_PINGROUP_ULPI_DATA3, + TEGRA_PINGROUP_ULPI_DATA4, + TEGRA_PINGROUP_ULPI_DATA5, + TEGRA_PINGROUP_ULPI_DATA6, + TEGRA_PINGROUP_ULPI_DATA7, + TEGRA_PINGROUP_ULPI_CLK, + TEGRA_PINGROUP_ULPI_DIR, + TEGRA_PINGROUP_ULPI_NXT, + TEGRA_PINGROUP_ULPI_STP, + TEGRA_PINGROUP_DAP3_FS, + TEGRA_PINGROUP_DAP3_DIN, + TEGRA_PINGROUP_DAP3_DOUT, + TEGRA_PINGROUP_DAP3_SCLK, + TEGRA_PINGROUP_GPIO_PV0, + TEGRA_PINGROUP_GPIO_PV1, + TEGRA_PINGROUP_SDMMC1_CLK, + TEGRA_PINGROUP_SDMMC1_CMD, + TEGRA_PINGROUP_SDMMC1_DAT3, + TEGRA_PINGROUP_SDMMC1_DAT2, + TEGRA_PINGROUP_SDMMC1_DAT1, + TEGRA_PINGROUP_SDMMC1_DAT0, + TEGRA_PINGROUP_GPIO_PV2, + TEGRA_PINGROUP_GPIO_PV3, + TEGRA_PINGROUP_CLK2_OUT, + TEGRA_PINGROUP_CLK2_REQ, + TEGRA_PINGROUP_LCD_PWR1, + TEGRA_PINGROUP_LCD_PWR2, + TEGRA_PINGROUP_LCD_SDIN, + TEGRA_PINGROUP_LCD_SDOUT, + TEGRA_PINGROUP_LCD_WR_N, + TEGRA_PINGROUP_LCD_CS0_N, + TEGRA_PINGROUP_LCD_DC0, + TEGRA_PINGROUP_LCD_SCK, + TEGRA_PINGROUP_LCD_PWR0, + TEGRA_PINGROUP_LCD_PCLK, + TEGRA_PINGROUP_LCD_DE, + TEGRA_PINGROUP_LCD_HSYNC, + TEGRA_PINGROUP_LCD_VSYNC, + TEGRA_PINGROUP_LCD_D0, + TEGRA_PINGROUP_LCD_D1, + TEGRA_PINGROUP_LCD_D2, + TEGRA_PINGROUP_LCD_D3, + TEGRA_PINGROUP_LCD_D4, + TEGRA_PINGROUP_LCD_D5, + TEGRA_PINGROUP_LCD_D6, + TEGRA_PINGROUP_LCD_D7, + TEGRA_PINGROUP_LCD_D8, + TEGRA_PINGROUP_LCD_D9, + TEGRA_PINGROUP_LCD_D10, + TEGRA_PINGROUP_LCD_D11, + TEGRA_PINGROUP_LCD_D12, + TEGRA_PINGROUP_LCD_D13, + TEGRA_PINGROUP_LCD_D14, + TEGRA_PINGROUP_LCD_D15, + TEGRA_PINGROUP_LCD_D16, + TEGRA_PINGROUP_LCD_D17, + TEGRA_PINGROUP_LCD_D18, + TEGRA_PINGROUP_LCD_D19, + TEGRA_PINGROUP_LCD_D20, + TEGRA_PINGROUP_LCD_D21, + TEGRA_PINGROUP_LCD_D22, + TEGRA_PINGROUP_LCD_D23, + TEGRA_PINGROUP_LCD_CS1_N, + TEGRA_PINGROUP_LCD_M1, + TEGRA_PINGROUP_LCD_DC1, + TEGRA_PINGROUP_HDMI_INT, + TEGRA_PINGROUP_DDC_SCL, + TEGRA_PINGROUP_DDC_SDA, + TEGRA_PINGROUP_CRT_HSYNC, + TEGRA_PINGROUP_CRT_VSYNC, + TEGRA_PINGROUP_VI_D0, + TEGRA_PINGROUP_VI_D1, + TEGRA_PINGROUP_VI_D2, + TEGRA_PINGROUP_VI_D3, + TEGRA_PINGROUP_VI_D4, + TEGRA_PINGROUP_VI_D5, + TEGRA_PINGROUP_VI_D6, + TEGRA_PINGROUP_VI_D7, + TEGRA_PINGROUP_VI_D8, + TEGRA_PINGROUP_VI_D9, + TEGRA_PINGROUP_VI_D10, + TEGRA_PINGROUP_VI_D11, + TEGRA_PINGROUP_VI_PCLK, + TEGRA_PINGROUP_VI_MCLK, + TEGRA_PINGROUP_VI_VSYNC, + TEGRA_PINGROUP_VI_HSYNC, + TEGRA_PINGROUP_UART2_RXD, + TEGRA_PINGROUP_UART2_TXD, + TEGRA_PINGROUP_UART2_RTS_N, + TEGRA_PINGROUP_UART2_CTS_N, + TEGRA_PINGROUP_UART3_TXD, + TEGRA_PINGROUP_UART3_RXD, + TEGRA_PINGROUP_UART3_CTS_N, + TEGRA_PINGROUP_UART3_RTS_N, + TEGRA_PINGROUP_GPIO_PU0, + TEGRA_PINGROUP_GPIO_PU1, + TEGRA_PINGROUP_GPIO_PU2, + TEGRA_PINGROUP_GPIO_PU3, + TEGRA_PINGROUP_GPIO_PU4, + TEGRA_PINGROUP_GPIO_PU5, + TEGRA_PINGROUP_GPIO_PU6, + TEGRA_PINGROUP_GEN1_I2C_SDA, + TEGRA_PINGROUP_GEN1_I2C_SCL, + TEGRA_PINGROUP_DAP4_FS, + TEGRA_PINGROUP_DAP4_DIN, + TEGRA_PINGROUP_DAP4_DOUT, + TEGRA_PINGROUP_DAP4_SCLK, + TEGRA_PINGROUP_CLK3_OUT, + TEGRA_PINGROUP_CLK3_REQ, + TEGRA_PINGROUP_GMI_WP_N, + TEGRA_PINGROUP_GMI_IORDY, + TEGRA_PINGROUP_GMI_WAIT, + TEGRA_PINGROUP_GMI_ADV_N, + TEGRA_PINGROUP_GMI_CLK, + TEGRA_PINGROUP_GMI_CS0_N, + TEGRA_PINGROUP_GMI_CS1_N, + TEGRA_PINGROUP_GMI_CS2_N, + TEGRA_PINGROUP_GMI_CS3_N, + TEGRA_PINGROUP_GMI_CS4_N, + TEGRA_PINGROUP_GMI_CS6_N, + TEGRA_PINGROUP_GMI_CS7_N, + TEGRA_PINGROUP_GMI_AD0, + TEGRA_PINGROUP_GMI_AD1, + TEGRA_PINGROUP_GMI_AD2, + TEGRA_PINGROUP_GMI_AD3, + TEGRA_PINGROUP_GMI_AD4, + TEGRA_PINGROUP_GMI_AD5, + TEGRA_PINGROUP_GMI_AD6, + TEGRA_PINGROUP_GMI_AD7, + TEGRA_PINGROUP_GMI_AD8, + TEGRA_PINGROUP_GMI_AD9, + TEGRA_PINGROUP_GMI_AD10, + TEGRA_PINGROUP_GMI_AD11, + TEGRA_PINGROUP_GMI_AD12, + TEGRA_PINGROUP_GMI_AD13, + TEGRA_PINGROUP_GMI_AD14, + TEGRA_PINGROUP_GMI_AD15, + TEGRA_PINGROUP_GMI_A16, + TEGRA_PINGROUP_GMI_A17, + TEGRA_PINGROUP_GMI_A18, + TEGRA_PINGROUP_GMI_A19, + TEGRA_PINGROUP_GMI_WR_N, + TEGRA_PINGROUP_GMI_OE_N, + TEGRA_PINGROUP_GMI_DQS, + TEGRA_PINGROUP_GMI_RST_N, + TEGRA_PINGROUP_GEN2_I2C_SCL, + TEGRA_PINGROUP_GEN2_I2C_SDA, + TEGRA_PINGROUP_SDMMC4_CLK, + TEGRA_PINGROUP_SDMMC4_CMD, + TEGRA_PINGROUP_SDMMC4_DAT0, + TEGRA_PINGROUP_SDMMC4_DAT1, + TEGRA_PINGROUP_SDMMC4_DAT2, + TEGRA_PINGROUP_SDMMC4_DAT3, + TEGRA_PINGROUP_SDMMC4_DAT4, + TEGRA_PINGROUP_SDMMC4_DAT5, + TEGRA_PINGROUP_SDMMC4_DAT6, + TEGRA_PINGROUP_SDMMC4_DAT7, + TEGRA_PINGROUP_SDMMC4_RST_N, + TEGRA_PINGROUP_CAM_MCLK, + TEGRA_PINGROUP_GPIO_PCC1, + TEGRA_PINGROUP_GPIO_PBB0, + TEGRA_PINGROUP_CAM_I2C_SCL, + TEGRA_PINGROUP_CAM_I2C_SDA, + TEGRA_PINGROUP_GPIO_PBB3, + TEGRA_PINGROUP_GPIO_PBB4, + TEGRA_PINGROUP_GPIO_PBB5, + TEGRA_PINGROUP_GPIO_PBB6, + TEGRA_PINGROUP_GPIO_PBB7, + TEGRA_PINGROUP_GPIO_PCC2, + TEGRA_PINGROUP_JTAG_RTCK, + TEGRA_PINGROUP_PWR_I2C_SCL, + TEGRA_PINGROUP_PWR_I2C_SDA, + TEGRA_PINGROUP_KB_ROW0, + TEGRA_PINGROUP_KB_ROW1, + TEGRA_PINGROUP_KB_ROW2, + TEGRA_PINGROUP_KB_ROW3, + TEGRA_PINGROUP_KB_ROW4, + TEGRA_PINGROUP_KB_ROW5, + TEGRA_PINGROUP_KB_ROW6, + TEGRA_PINGROUP_KB_ROW7, + TEGRA_PINGROUP_KB_ROW8, + TEGRA_PINGROUP_KB_ROW9, + TEGRA_PINGROUP_KB_ROW10, + TEGRA_PINGROUP_KB_ROW11, + TEGRA_PINGROUP_KB_ROW12, + TEGRA_PINGROUP_KB_ROW13, + TEGRA_PINGROUP_KB_ROW14, + TEGRA_PINGROUP_KB_ROW15, + TEGRA_PINGROUP_KB_COL0, + TEGRA_PINGROUP_KB_COL1, + TEGRA_PINGROUP_KB_COL2, + TEGRA_PINGROUP_KB_COL3, + TEGRA_PINGROUP_KB_COL4, + TEGRA_PINGROUP_KB_COL5, + TEGRA_PINGROUP_KB_COL6, + TEGRA_PINGROUP_KB_COL7, + TEGRA_PINGROUP_CLK_32K_OUT, + TEGRA_PINGROUP_SYS_CLK_REQ, + TEGRA_PINGROUP_CORE_PWR_REQ, + TEGRA_PINGROUP_CPU_PWR_REQ, + TEGRA_PINGROUP_PWR_INT_N, + TEGRA_PINGROUP_CLK_32K_IN, + TEGRA_PINGROUP_OWR, + TEGRA_PINGROUP_DAP1_FS, + TEGRA_PINGROUP_DAP1_DIN, + TEGRA_PINGROUP_DAP1_DOUT, + TEGRA_PINGROUP_DAP1_SCLK, + TEGRA_PINGROUP_CLK1_REQ, + TEGRA_PINGROUP_CLK1_OUT, + TEGRA_PINGROUP_SPDIF_IN, + TEGRA_PINGROUP_SPDIF_OUT, + TEGRA_PINGROUP_DAP2_FS, + TEGRA_PINGROUP_DAP2_DIN, + TEGRA_PINGROUP_DAP2_DOUT, + TEGRA_PINGROUP_DAP2_SCLK, + TEGRA_PINGROUP_SPI2_MOSI, + TEGRA_PINGROUP_SPI2_MISO, + TEGRA_PINGROUP_SPI2_CS0_N, + TEGRA_PINGROUP_SPI2_SCK, + TEGRA_PINGROUP_SPI1_MOSI, + TEGRA_PINGROUP_SPI1_SCK, + TEGRA_PINGROUP_SPI1_CS0_N, + TEGRA_PINGROUP_SPI1_MISO, + TEGRA_PINGROUP_SPI2_CS1_N, + TEGRA_PINGROUP_SPI2_CS2_N, + TEGRA_PINGROUP_SDMMC3_CLK, + TEGRA_PINGROUP_SDMMC3_CMD, + TEGRA_PINGROUP_SDMMC3_DAT0, + TEGRA_PINGROUP_SDMMC3_DAT1, + TEGRA_PINGROUP_SDMMC3_DAT2, + TEGRA_PINGROUP_SDMMC3_DAT3, + TEGRA_PINGROUP_SDMMC3_DAT4, + TEGRA_PINGROUP_SDMMC3_DAT5, + TEGRA_PINGROUP_SDMMC3_DAT6, + TEGRA_PINGROUP_SDMMC3_DAT7, + TEGRA_PINGROUP_PEX_L0_PRSNT_N, + TEGRA_PINGROUP_PEX_L0_RST_N, + TEGRA_PINGROUP_PEX_L0_CLKREQ_N, + TEGRA_PINGROUP_PEX_WAKE_N, + TEGRA_PINGROUP_PEX_L1_PRSNT_N, + TEGRA_PINGROUP_PEX_L1_RST_N, + TEGRA_PINGROUP_PEX_L1_CLKREQ_N, + TEGRA_PINGROUP_PEX_L2_PRSNT_N, + TEGRA_PINGROUP_PEX_L2_RST_N, + TEGRA_PINGROUP_PEX_L2_CLKREQ_N, + TEGRA_PINGROUP_HDMI_CEC, + TEGRA_MAX_PINGROUP, +}; + +enum tegra_drive_pingroup { + TEGRA_DRIVE_PINGROUP_AO1 = 0, + TEGRA_DRIVE_PINGROUP_AO2, + TEGRA_DRIVE_PINGROUP_AT1, + TEGRA_DRIVE_PINGROUP_AT2, + TEGRA_DRIVE_PINGROUP_AT3, + TEGRA_DRIVE_PINGROUP_AT4, + TEGRA_DRIVE_PINGROUP_AT5, + TEGRA_DRIVE_PINGROUP_CDEV1, + TEGRA_DRIVE_PINGROUP_CDEV2, + TEGRA_DRIVE_PINGROUP_CSUS, + TEGRA_DRIVE_PINGROUP_DAP1, + TEGRA_DRIVE_PINGROUP_DAP2, + TEGRA_DRIVE_PINGROUP_DAP3, + TEGRA_DRIVE_PINGROUP_DAP4, + TEGRA_DRIVE_PINGROUP_DBG, + TEGRA_DRIVE_PINGROUP_LCD1, + TEGRA_DRIVE_PINGROUP_LCD2, + TEGRA_DRIVE_PINGROUP_SDIO2, + TEGRA_DRIVE_PINGROUP_SDIO3, + TEGRA_DRIVE_PINGROUP_SPI, + TEGRA_DRIVE_PINGROUP_UAA, + TEGRA_DRIVE_PINGROUP_UAB, + TEGRA_DRIVE_PINGROUP_UART2, + TEGRA_DRIVE_PINGROUP_UART3, + TEGRA_DRIVE_PINGROUP_VI1, + TEGRA_DRIVE_PINGROUP_SDIO1, + TEGRA_DRIVE_PINGROUP_CRT, + TEGRA_DRIVE_PINGROUP_DDC, + TEGRA_DRIVE_PINGROUP_GMA, + TEGRA_DRIVE_PINGROUP_GMB, + TEGRA_DRIVE_PINGROUP_GMC, + TEGRA_DRIVE_PINGROUP_GMD, + TEGRA_DRIVE_PINGROUP_GME, + TEGRA_DRIVE_PINGROUP_GMF, + TEGRA_DRIVE_PINGROUP_GMG, + TEGRA_DRIVE_PINGROUP_GMH, + TEGRA_DRIVE_PINGROUP_OWR, + TEGRA_DRIVE_PINGROUP_UAD, + TEGRA_DRIVE_PINGROUP_GPV, + TEGRA_DRIVE_PINGROUP_DEV3, + TEGRA_DRIVE_PINGROUP_CEC, + TEGRA_MAX_DRIVE_PINGROUP, +}; + +#endif + diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index 988c6c5..055f179 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -24,6 +24,7 @@ enum tegra_mux_func { TEGRA_MUX_RSVD2 = 0x8001, TEGRA_MUX_RSVD3 = 0x8002, TEGRA_MUX_RSVD4 = 0x8003, + TEGRA_MUX_INVALID = 0x4000, TEGRA_MUX_NONE = -1, TEGRA_MUX_AHB_CLK, TEGRA_MUX_APB_CLK, @@ -85,6 +86,49 @@ enum tegra_mux_func { TEGRA_MUX_VI, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_MUX_XIO, + TEGRA_MUX_BLINK, + TEGRA_MUX_CEC, + TEGRA_MUX_CLK12, + TEGRA_MUX_DAP, + TEGRA_MUX_DAPSDMMC2, + TEGRA_MUX_DDR, + TEGRA_MUX_DEV3, + TEGRA_MUX_DTV, + TEGRA_MUX_VI_ALT1, + TEGRA_MUX_VI_ALT2, + TEGRA_MUX_VI_ALT3, + TEGRA_MUX_EMC_DLL, + TEGRA_MUX_EXTPERIPH1, + TEGRA_MUX_EXTPERIPH2, + TEGRA_MUX_EXTPERIPH3, + TEGRA_MUX_GMI_ALT, + TEGRA_MUX_HDA, + TEGRA_MUX_HSI, + TEGRA_MUX_I2C4, + TEGRA_MUX_I2C5, + TEGRA_MUX_I2CPWR, + TEGRA_MUX_I2S0, + TEGRA_MUX_I2S1, + TEGRA_MUX_I2S2, + TEGRA_MUX_I2S3, + TEGRA_MUX_I2S4, + TEGRA_MUX_NAND_ALT, + TEGRA_MUX_POPSDIO4, + TEGRA_MUX_POPSDMMC4, + TEGRA_MUX_PWM0, + TEGRA_MUX_PWM1, + TEGRA_MUX_PWM2, + TEGRA_MUX_PWM3, + TEGRA_MUX_SATA, + TEGRA_MUX_SPI5, + TEGRA_MUX_SPI6, + TEGRA_MUX_SYSCLK, + TEGRA_MUX_VGP1, + TEGRA_MUX_VGP2, + TEGRA_MUX_VGP3, + TEGRA_MUX_VGP4, + TEGRA_MUX_VGP5, + TEGRA_MUX_VGP6, TEGRA_MUX_SAFE, TEGRA_MAX_MUX, }; @@ -115,6 +159,12 @@ enum tegra_vddio { TEGRA_VDDIO_SYS, TEGRA_VDDIO_AUDIO, TEGRA_VDDIO_SD, + TEGRA_VDDIO_CAM, + TEGRA_VDDIO_GMI, + TEGRA_VDDIO_PEXCTL, + TEGRA_VDDIO_SDMMC1, + TEGRA_VDDIO_SDMMC3, + TEGRA_VDDIO_SDMMC4, }; struct tegra_pingroup_config { @@ -230,6 +280,9 @@ typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); +void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, + const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); + int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate); int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd); diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c new file mode 100644 index 0000000..8b6db9a --- /dev/null +++ b/arch/arm/mach-tegra/pinmux-tegra30-tables.c @@ -0,0 +1,376 @@ +/* + * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c + * + * Common pinmux configurations for Tegra30 SoCs + * + * Copyright (C) 2010,2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/string.h> + +#include <mach/iomap.h> +#include <mach/pinmux.h> +#include <mach/pinmux-tegra30.h> +#include <mach/suspend.h> + +#define PINGROUP_REG_A 0x868 +#define MUXCTL_REG_A 0x3000 + +#define DRIVE_PINGROUP(pg_name, r) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg_bank = 0, \ + .reg = ((r) - PINGROUP_REG_A) \ + } + +static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { + DRIVE_PINGROUP(AO1, 0x868), + DRIVE_PINGROUP(AO2, 0x86c), + DRIVE_PINGROUP(AT1, 0x870), + DRIVE_PINGROUP(AT2, 0x874), + DRIVE_PINGROUP(AT3, 0x878), + DRIVE_PINGROUP(AT4, 0x87c), + DRIVE_PINGROUP(AT5, 0x880), + DRIVE_PINGROUP(CDEV1, 0x884), + DRIVE_PINGROUP(CDEV2, 0x888), + DRIVE_PINGROUP(CSUS, 0x88c), + DRIVE_PINGROUP(DAP1, 0x890), + DRIVE_PINGROUP(DAP2, 0x894), + DRIVE_PINGROUP(DAP3, 0x898), + DRIVE_PINGROUP(DAP4, 0x89c), + DRIVE_PINGROUP(DBG, 0x8a0), + DRIVE_PINGROUP(LCD1, 0x8a4), + DRIVE_PINGROUP(LCD2, 0x8a8), + DRIVE_PINGROUP(SDIO2, 0x8ac), + DRIVE_PINGROUP(SDIO3, 0x8b0), + DRIVE_PINGROUP(SPI, 0x8b4), + DRIVE_PINGROUP(UAA, 0x8b8), + DRIVE_PINGROUP(UAB, 0x8bc), + DRIVE_PINGROUP(UART2, 0x8c0), + DRIVE_PINGROUP(UART3, 0x8c4), + DRIVE_PINGROUP(VI1, 0x8c8), + DRIVE_PINGROUP(SDIO1, 0x8ec), + DRIVE_PINGROUP(CRT, 0x8f8), + DRIVE_PINGROUP(DDC, 0x8fc), + DRIVE_PINGROUP(GMA, 0x900), + DRIVE_PINGROUP(GMB, 0x904), + DRIVE_PINGROUP(GMC, 0x908), + DRIVE_PINGROUP(GMD, 0x90c), + DRIVE_PINGROUP(GME, 0x910), + DRIVE_PINGROUP(GMF, 0x914), + DRIVE_PINGROUP(GMG, 0x918), + DRIVE_PINGROUP(GMH, 0x91c), + DRIVE_PINGROUP(OWR, 0x920), + DRIVE_PINGROUP(UAD, 0x924), + DRIVE_PINGROUP(GPV, 0x928), + DRIVE_PINGROUP(DEV3, 0x92c), + DRIVE_PINGROUP(CEC, 0x938), +}; + +#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \ + [TEGRA_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .vddio = TEGRA_VDDIO_ ## vdd, \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_ ## f2, \ + TEGRA_MUX_ ## f3, \ + }, \ + .func_safe = TEGRA_MUX_ ## fs, \ + .tri_bank = 1, \ + .tri_reg = ((reg) - MUXCTL_REG_A), \ + .tri_bit = 4, \ + .mux_bank = 1, \ + .mux_reg = ((reg) - MUXCTL_REG_A), \ + .mux_bit = 0, \ + .pupd_bank = 1, \ + .pupd_reg = ((reg) - MUXCTL_REG_A), \ + .pupd_bit = 2, \ + .io_default = TEGRA_PIN_ ## iod, \ + .od_bit = 6, \ + .lock_bit = 7, \ + .ioreset_bit = 8, \ + } + +static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { + /* NAME VDD f0 f1 f2 f3 fSafe io reg */ + PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000), + PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004), + PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008), + PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c), + PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010), + PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014), + PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018), + PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c), + PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020), + PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024), + PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028), + PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c), + PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030), + PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034), + PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038), + PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c), + PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040), + PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044), + PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048), + PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c), + PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050), + PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054), + PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058), + PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c), + PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060), + PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064), + PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068), + PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c), + PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070), + PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074), + PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078), + PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c), + PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080), + PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084), + PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088), + PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c), + PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090), + PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094), + PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098), + PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c), + PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0), + PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4), + PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8), + PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac), + PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0), + PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4), + PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8), + PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc), + PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0), + PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4), + PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8), + PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc), + PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0), + PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4), + PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8), + PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc), + PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0), + PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4), + PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8), + PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec), + PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0), + PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4), + PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8), + PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc), + PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100), + PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104), + PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108), + PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c), + PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110), + PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114), + PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118), + PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c), + PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120), + PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124), + PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128), + PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c), + PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130), + PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134), + PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138), + PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c), + PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140), + PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144), + PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148), + PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c), + PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150), + PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154), + PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158), + PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c), + PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160), + PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164), + PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168), + PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c), + PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170), + PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174), + PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178), + PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c), + PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180), + PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184), + PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188), + PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c), + PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190), + PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194), + PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198), + PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c), + PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0), + PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4), + PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8), + PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac), + PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0), + PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4), + PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8), + PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc), + PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0), + PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4), + PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8), + PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc), + PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0), + PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4), + PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8), + PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc), + PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0), + PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4), + PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8), + PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec), + PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0), + PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4), + PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8), + PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc), + PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200), + PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204), + PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208), + PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c), + PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210), + PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214), + PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218), + PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c), + PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220), + PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224), + PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228), + PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c), + PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230), + PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234), + PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238), + PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c), + PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240), + PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244), + PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248), + PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c), + PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250), + PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254), + PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258), + PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c), + PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260), + PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264), + PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268), + PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c), + PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270), + PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274), + PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278), + PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c), + PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280), + PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284), + PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288), + PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c), + PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290), + PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294), + PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298), + PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c), + PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0), + PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4), + PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8), + PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac), + PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0), + PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4), + PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8), + PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc), + PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0), + PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4), + PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8), + PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc), + PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0), + PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4), + PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8), + PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc), + PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0), + PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4), + PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8), + PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec), + PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0), + PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4), + PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8), + PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc), + PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300), + PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304), + PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308), + PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c), + PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310), + PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314), + PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318), + PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c), + PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320), + PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324), + PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328), + PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c), + PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330), + PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334), + PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338), + PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c), + PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340), + PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344), + PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348), + PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c), + PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350), + PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354), + PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358), + PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c), + PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360), + PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364), + PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368), + PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c), + PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370), + PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374), + PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378), + PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c), + PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380), + PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384), + PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388), + PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c), + PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390), + PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394), + PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398), + PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c), + PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0), + PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4), + PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8), + PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac), + PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0), + PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4), + PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8), + PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc), + PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0), + PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4), + PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8), + PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc), + PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0), + PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4), + PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8), + PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc), + PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0), +}; + +void __init tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max) +{ + *pg = tegra_soc_pingroups; + *pg_max = TEGRA_MAX_PINGROUP; + *pgdrive = tegra_soc_drive_pingroups; + *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP; +} + diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 0682e6e..52a6126 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -102,6 +102,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = { [TEGRA_MUX_VI] = "VI", [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", [TEGRA_MUX_XIO] = "XIO", + [TEGRA_MUX_BLINK] = "BLINK", + [TEGRA_MUX_CEC] = "CEC", + [TEGRA_MUX_CLK12] = "CLK12", + [TEGRA_MUX_DAP] = "DAP", + [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2", + [TEGRA_MUX_DDR] = "DDR", + [TEGRA_MUX_DEV3] = "DEV3", + [TEGRA_MUX_DTV] = "DTV", + [TEGRA_MUX_VI_ALT1] = "VI_ALT1", + [TEGRA_MUX_VI_ALT2] = "VI_ALT2", + [TEGRA_MUX_VI_ALT3] = "VI_ALT3", + [TEGRA_MUX_EMC_DLL] = "EMC_DLL", + [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1", + [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2", + [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3", + [TEGRA_MUX_GMI_ALT] = "GMI_ALT", + [TEGRA_MUX_HDA] = "HDA", + [TEGRA_MUX_HSI] = "HSI", + [TEGRA_MUX_I2C4] = "I2C4", + [TEGRA_MUX_I2C5] = "I2C5", + [TEGRA_MUX_I2CPWR] = "I2CPWR", + [TEGRA_MUX_I2S0] = "I2S0", + [TEGRA_MUX_I2S1] = "I2S1", + [TEGRA_MUX_I2S2] = "I2S2", + [TEGRA_MUX_I2S3] = "I2S3", + [TEGRA_MUX_I2S4] = "I2S4", + [TEGRA_MUX_NAND_ALT] = "NAND_ALT", + [TEGRA_MUX_POPSDIO4] = "POPSDIO4", + [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4", + [TEGRA_MUX_PWM0] = "PWM0", + [TEGRA_MUX_PWM1] = "PWM2", + [TEGRA_MUX_PWM2] = "PWM2", + [TEGRA_MUX_PWM3] = "PWM3", + [TEGRA_MUX_SATA] = "SATA", + [TEGRA_MUX_SPI5] = "SPI5", + [TEGRA_MUX_SPI6] = "SPI6", + [TEGRA_MUX_SYSCLK] = "SYSCLK", + [TEGRA_MUX_VGP1] = "VGP1", + [TEGRA_MUX_VGP2] = "VGP2", + [TEGRA_MUX_VGP3] = "VGP3", + [TEGRA_MUX_VGP4] = "VGP4", + [TEGRA_MUX_VGP5] = "VGP5", + [TEGRA_MUX_VGP6] = "VGP6", [TEGRA_MUX_SAFE] = "<safe>", }; @@ -669,7 +712,12 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co } static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { +#ifdef CONFIG_ARCH_TEGRA_2x_SOC { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init }, +#endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init }, +#endif { }, }; -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 10/10] arm/tegra: add support for tegra30 based board cardhu [not found] ` <1321010541-31337-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> ` (2 preceding siblings ...) 2011-11-11 11:22 ` [PATCH v4 08/10] arm/tegra: pinmux tables and definitions for tegra30 Peter De Schrijver @ 2011-11-11 11:22 ` Peter De Schrijver 3 siblings, 0 replies; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, Stephen Warren, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-tegra-u79uwXL29TY76Z2rM5mHXA Add support for the tegra30 based cardhu development board. Cardhu is a tablet formfactor reference design for tegra30. The patch provides a device tree for the board, updates Makefile.boot to build the dtb, includes the platform in Kconfig and updates board-dt.c. Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- arch/arm/boot/dts/tegra-cardhu.dts | 36 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/Kconfig | 7 +++++++ arch/arm/mach-tegra/Makefile.boot | 1 + arch/arm/mach-tegra/board-dt.c | 1 + 4 files changed, 45 insertions(+), 0 deletions(-) create mode 100644 arch/arm/boot/dts/tegra-cardhu.dts diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts new file mode 100644 index 0000000..70c41fc --- /dev/null +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = < 0x80000000 0x40000000 >; + }; + + serial@70006000 { + clock-frequency = < 408000000 >; + }; + + i2c@7000c000 { + clock-frequency = <100000>; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + }; + + i2c@7000c700 { + clock-frequency = <100000>; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + }; +}; diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index aad54ca..6bae1bb 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -91,6 +91,13 @@ config MACH_VENTANA help Support for the nVidia Ventana development platform +config MACH_CARDHU + bool "Cardhu board" + depends on ARCH_TEGRA_3x_SOC + select MACH_TEGRA_DT + help + Support for the NVIDIA Cardhu development platform + choice prompt "Low-level debug console UART" default TEGRA_DEBUG_UART_NONE diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index bd12c9f..b518848 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -5,3 +5,4 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb +dtb-$(CONFIG_MACH_CARDHU) += tegra-cardhu.dtb diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index 486b473..7f3b235 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -146,6 +146,7 @@ static const char * tegra_dt_board_compat[] = { "nvidia,harmony", "nvidia,seaboard", "nvidia,ventana", + "nvidia,cardhu", NULL }; -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 06/10] arm/tegra: prepare pinmux code for multiple tegra variants 2011-11-11 11:22 [PATCH v4 00/10] Add support for tegra30 and cardhu Peter De Schrijver ` (3 preceding siblings ...) [not found] ` <1321010541-31337-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2011-11-11 11:22 ` Peter De Schrijver [not found] ` <1321010541-31337-7-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2011-11-11 11:22 ` [PATCH v4 07/10] arm/tegra: add new fields to struct tegra_pingroup_desc Peter De Schrijver ` (2 subsequent siblings) 7 siblings, 1 reply; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Stephen Warren, linux-kernel, linux-tegra, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel This patch modifies the pinmux code to be useable for multiple tegra variants. Some tegra20 specific constants will be replaced by variables which will be initialized to the appropriate value at runtime. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- arch/arm/mach-tegra/board-harmony-pcie.c | 1 + arch/arm/mach-tegra/board-harmony-pinmux.c | 1 + arch/arm/mach-tegra/board-paz00-pinmux.c | 1 + arch/arm/mach-tegra/board-trimslice-pinmux.c | 1 + arch/arm/mach-tegra/include/mach/pinmux.h | 25 +++---- arch/arm/mach-tegra/pinmux-tegra20-tables.c | 15 +++- arch/arm/mach-tegra/pinmux.c | 109 +++++++++++++++----------- 7 files changed, 90 insertions(+), 63 deletions(-) diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index 6db7d69..bd402d0 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c @@ -23,6 +23,7 @@ #include <asm/mach-types.h> #include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> #include "board.h" #include "board-harmony.h" diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c index e99b456..286253f 100644 --- a/arch/arm/mach-tegra/board-harmony-pinmux.c +++ b/arch/arm/mach-tegra/board-harmony-pinmux.c @@ -17,6 +17,7 @@ #include <linux/kernel.h> #include <linux/gpio.h> #include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> #include "gpio-names.h" #include "board-harmony.h" diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c index fb20894..484dbd6 100644 --- a/arch/arm/mach-tegra/board-paz00-pinmux.c +++ b/arch/arm/mach-tegra/board-paz00-pinmux.c @@ -17,6 +17,7 @@ #include <linux/kernel.h> #include <linux/gpio.h> #include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> #include "gpio-names.h" #include "board-paz00.h" diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c index 4969dd2..cc9d4f4 100644 --- a/arch/arm/mach-tegra/board-trimslice-pinmux.c +++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c @@ -18,6 +18,7 @@ #include <linux/init.h> #include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> #include "gpio-names.h" #include "board-trimslice.h" diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index b93df9e..35999ce 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -17,12 +17,6 @@ #ifndef __MACH_TEGRA_PINMUX_H #define __MACH_TEGRA_PINMUX_H -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) -#include "pinmux-tegra20.h" -#else -#error "Undefined Tegra architecture" -#endif - enum tegra_mux_func { TEGRA_MUX_RSVD = 0x8000, TEGRA_MUX_RSVD1 = 0x8000, @@ -118,7 +112,7 @@ enum tegra_vddio { }; struct tegra_pingroup_config { - enum tegra_pingroup pingroup; + int pingroup; enum tegra_mux_func func; enum tegra_pullupdown pupd; enum tegra_tristate tristate; @@ -187,7 +181,7 @@ enum tegra_schmitt { }; struct tegra_drive_pingroup_config { - enum tegra_drive_pingroup pingroup; + int pingroup; enum tegra_hsm hsm; enum tegra_schmitt schmitt; enum tegra_drive drive; @@ -219,13 +213,15 @@ struct tegra_pingroup_desc { s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ }; -extern const struct tegra_pingroup_desc tegra_soc_pingroups[]; -extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[]; +typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max); -int tegra_pinmux_set_tristate(enum tegra_pingroup pg, - enum tegra_tristate tristate); -int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, - enum tegra_pullupdown pupd); +void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, + const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); + +int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate); +int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd); void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len); @@ -241,4 +237,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, int len, enum tegra_pullupdown pupd); #endif - diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c index 88642a5..efe6aee 100644 --- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c +++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -44,7 +44,7 @@ .reg = ((r) - PINGROUP_REG_A) \ } -const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { +static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { DRIVE_PINGROUP(AO1, 0x868), DRIVE_PINGROUP(AO2, 0x86c), DRIVE_PINGROUP(AT1, 0x870), @@ -108,7 +108,7 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE .pupd_bit = pupd_b, \ } -const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { +static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), @@ -227,3 +227,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), }; + +void __init tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max) +{ + *pg = tegra_soc_pingroups; + *pg_max = TEGRA_MAX_PINGROUP; + *pgdrive = tegra_soc_drive_pingroups; + *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP; +} + diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 1d20165..0682e6e 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -21,6 +21,9 @@ #include <linux/spinlock.h> #include <linux/io.h> #include <linux/platform_device.h> +#ifdef CONFIG_OF +#include <linux/of_platform.h> +#endif #include <mach/iomap.h> #include <mach/pinmux.h> @@ -33,8 +36,10 @@ #define SLWR(reg) (((reg) >> 28) & 0x3) #define SLWF(reg) (((reg) >> 30) & 0x3) -static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups; -static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups; +static const struct tegra_pingroup_desc *pingroups; +static const struct tegra_drive_pingroup_desc *drive_pingroups; +static int pingroup_max; +static int drive_max; static char *tegra_mux_names[TEGRA_MAX_MUX] = { [TEGRA_MUX_AHB_CLK] = "AHB_CLK", @@ -116,9 +121,9 @@ static const char *tegra_slew_names[TEGRA_MAX_SLEW] = { static DEFINE_SPINLOCK(mux_lock); -static const char *pingroup_name(enum tegra_pingroup pg) +static const char *pingroup_name(int pg) { - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return "<UNKNOWN>"; return pingroups[pg].name; @@ -189,10 +194,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) int i; unsigned long reg; unsigned long flags; - enum tegra_pingroup pg = config->pingroup; + int pg = config->pingroup; enum tegra_mux_func func = config->func; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].mux_reg < 0) @@ -230,13 +235,12 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) return 0; } -int tegra_pinmux_set_tristate(enum tegra_pingroup pg, - enum tegra_tristate tristate) +int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate) { unsigned long reg; unsigned long flags; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].tri_reg < 0) @@ -255,13 +259,12 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg, return 0; } -int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, - enum tegra_pullupdown pupd) +int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd) { unsigned long reg; unsigned long flags; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].pupd_reg < 0) @@ -287,7 +290,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config) { - enum tegra_pingroup pingroup = config->pingroup; + int pingroup = config->pingroup; enum tegra_mux_func func = config->func; enum tegra_pullupdown pupd = config->pupd; enum tegra_tristate tristate = config->tristate; @@ -323,9 +326,9 @@ void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int l tegra_pinmux_config_pingroup(&config[i]); } -static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) +static const char *drive_pinmux_name(int pg) { - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return "<UNKNOWN>"; return drive_pingroups[pg].name; @@ -352,12 +355,11 @@ static const char *slew_name(unsigned long val) return tegra_slew_names[val]; } -static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, - enum tegra_hsm hsm) +static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE) @@ -377,12 +379,11 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, - enum tegra_schmitt schmitt) +static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE) @@ -402,12 +403,11 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, - enum tegra_drive drive) +static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (drive < 0 || drive >= TEGRA_MAX_DRIVE) @@ -425,12 +425,12 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_pull_down(int pg, enum tegra_pull_strength pull_down) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL) @@ -448,12 +448,12 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_pull_up(int pg, enum tegra_pull_strength pull_up) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL) @@ -471,12 +471,12 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_slew_rising(int pg, enum tegra_slew slew_rising) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW) @@ -494,12 +494,12 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_slew_falling(int pg, enum tegra_slew slew_falling) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW) @@ -517,7 +517,7 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, return 0; } -static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup, +static void tegra_drive_pinmux_config_pingroup(int pingroup, enum tegra_hsm hsm, enum tegra_schmitt schmitt, enum tegra_drive drive, @@ -596,7 +596,7 @@ void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *conf for (i = 0; i < len; i++) { int err; c = config[i]; - if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) { + if (c.pingroup < 0 || c.pingroup >= pingroup_max) { WARN_ON(1); continue; } @@ -617,7 +617,7 @@ void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config for (i = 0; i < len; i++) { int err; if (config[i].pingroup < 0 || - config[i].pingroup >= TEGRA_MAX_PINGROUP) { + config[i].pingroup >= pingroup_max) { WARN_ON(1); continue; } @@ -635,7 +635,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf { int i; int err; - enum tegra_pingroup pingroup; + int pingroup; for (i = 0; i < len; i++) { pingroup = config[i].pingroup; @@ -654,7 +654,7 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co { int i; int err; - enum tegra_pingroup pingroup; + int pingroup; for (i = 0; i < len; i++) { pingroup = config[i].pingroup; @@ -668,11 +668,33 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co } } +static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { + { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init }, + { }, +}; + static int __devinit tegra_pinmux_probe(struct platform_device *pdev) { struct resource *res; int i; int config_bad = 0; + const struct of_device_id *match = NULL; + +#ifdef CONFIG_OF + match = of_match_device(tegra_pinmux_of_match, &pdev->dev); +#endif + + if (match) + ((pinmux_init)(match->data))(&pingroups, &pingroup_max, + &drive_pingroups, &drive_max); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + else + /* no device tree available, so we must be on tegra20 */ + tegra20_pinmux_init(&pingroups, &pingroup_max, + &drive_pingroups, &drive_max); +#else + pr_warn("non Tegra20 platform requires pinmux devicetree node\n"); +#endif for (i = 0; ; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); @@ -681,7 +703,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) } nbanks = i; - for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { + for (i = 0; i < pingroup_max; i++) { if (pingroups[i].tri_bank >= nbanks) { dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i); config_bad = 1; @@ -698,7 +720,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) } } - for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { + for (i = 0; i < drive_max; i++) { if (drive_pingroups[i].reg_bank >= nbanks) { dev_err(&pdev->dev, "drive pingroup %d: bad reg_bank\n", i); @@ -741,11 +763,6 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) return 0; } -static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { - { .compatible = "nvidia,tegra20-pinmux", }, - { }, -}; - static struct platform_driver tegra_pinmux_driver = { .driver = { .name = "tegra-pinmux", @@ -779,7 +796,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) int i; int len; - for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { + for (i = 0; i < pingroup_max; i++) { unsigned long reg; unsigned long tri; unsigned long mux; @@ -850,7 +867,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) int i; int len; - for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { + for (i = 0; i < drive_max; i++) { u32 reg; seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s", -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
[parent not found: <1321010541-31337-7-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* RE: [PATCH v4 06/10] arm/tegra: prepare pinmux code for multiple tegra variants [not found] ` <1321010541-31337-7-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2011-11-11 22:00 ` Stephen Warren 0 siblings, 0 replies; 23+ messages in thread From: Stephen Warren @ 2011-11-11 22:00 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Peter De Schrijver wrote at Friday, November 11, 2011 4:22 AM: > This patch modifies the pinmux code to be useable for multiple tegra variants. > Some tegra20 specific constants will be replaced by variables which will be > initialized to the appropriate value at runtime. > diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c > +#ifdef CONFIG_OF > +#include <linux/of_platform.h> > +#endif No need to ifdef the include. > +#ifdef CONFIG_OF > + match = of_match_device(tegra_pinmux_of_match, &pdev->dev); > +#endif There's already a dummy of_match_device that returns NULL if !CONFIG_OF, so you can avoid this ifdef. (at least in next-20111111). -- nvpublic ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v4 07/10] arm/tegra: add new fields to struct tegra_pingroup_desc 2011-11-11 11:22 [PATCH v4 00/10] Add support for tegra30 and cardhu Peter De Schrijver ` (4 preceding siblings ...) 2011-11-11 11:22 ` [PATCH v4 06/10] arm/tegra: prepare pinmux code for multiple tegra variants Peter De Schrijver @ 2011-11-11 11:22 ` Peter De Schrijver 2011-11-11 11:22 ` [PATCH v4 09/10] arm/tegra: implement support for tegra30 Peter De Schrijver 2011-11-11 21:40 ` [PATCH v4 00/10] Add support for tegra30 and cardhu Stephen Warren 7 siblings, 0 replies; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Stephen Warren, linux-kernel, linux-tegra, Colin Cross, Olof Johansson, Russell King, linux-arm-kernel Add new fields to struct tegra_pingroup_desc to support new hardware features introduced in the tegra30 SoC. The pinmux driver won't use those fields yet, but the tegra30 pinmux tables will already provide the necessary data. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- arch/arm/mach-tegra/include/mach/pinmux.h | 10 ++++++++++ arch/arm/mach-tegra/pinmux-tegra20-tables.c | 4 ++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index 35999ce..988c6c5 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -2,6 +2,7 @@ * linux/arch/arm/mach-tegra/include/mach/pinmux.h * * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010,2011 Nvidia, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -99,6 +100,11 @@ enum tegra_tristate { TEGRA_TRI_TRISTATE = 1, }; +enum tegra_pin_io { + TEGRA_PIN_OUTPUT = 0, + TEGRA_PIN_INPUT = 1, +}; + enum tegra_vddio { TEGRA_VDDIO_BB = 0, TEGRA_VDDIO_LCD, @@ -202,6 +208,7 @@ struct tegra_pingroup_desc { int funcs[4]; int func_safe; int vddio; + enum tegra_pin_io io_default; s16 tri_bank; /* Register bank the tri_reg exists within */ s16 mux_bank; /* Register bank the mux_reg exists within */ s16 pupd_bank; /* Register bank the pupd_reg exists within */ @@ -211,6 +218,9 @@ struct tegra_pingroup_desc { s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ + s8 lock_bit; /* offset of the LOCK bit into mux register bit */ + s8 od_bit; /* offset of the OD bit into mux register bit */ + s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */ }; typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c index efe6aee..0fe5335 100644 --- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c +++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -106,6 +106,10 @@ static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MA .pupd_bank = 2, \ .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ .pupd_bit = pupd_b, \ + .lock_bit = -1, \ + .od_bit = -1, \ + .ioreset_bit = -1, \ + .io_default = -1, \ } static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 09/10] arm/tegra: implement support for tegra30 2011-11-11 11:22 [PATCH v4 00/10] Add support for tegra30 and cardhu Peter De Schrijver ` (5 preceding siblings ...) 2011-11-11 11:22 ` [PATCH v4 07/10] arm/tegra: add new fields to struct tegra_pingroup_desc Peter De Schrijver @ 2011-11-11 11:22 ` Peter De Schrijver [not found] ` <1321010541-31337-10-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2011-11-11 21:40 ` [PATCH v4 00/10] Add support for tegra30 and cardhu Stephen Warren 7 siblings, 1 reply; 23+ messages in thread From: Peter De Schrijver @ 2011-11-11 11:22 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, Stephen Warren, linux-arm-kernel, linux-kernel, linux-tegra Add support for tegra30 SoC. This includes a device tree compatible type for this SoC ("nvidia,tegra30") and adds L2 cache initialization for this new SoC. The clock framework is still missing, which prevents most drivers from working. The basic IRQs are the same, so remove the dependency on CONFIG_ARCH_TEGRA_2x_SOC. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- arch/arm/mach-tegra/Kconfig | 18 +++++++++++++----- arch/arm/mach-tegra/board-dt.c | 3 +++ arch/arm/mach-tegra/board.h | 3 +++ arch/arm/mach-tegra/common.c | 7 +++++++ arch/arm/mach-tegra/include/mach/irqs.h | 2 -- 5 files changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 2b1d49b..aad54ca 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -2,11 +2,8 @@ if ARCH_TEGRA comment "NVIDIA Tegra options" -choice - prompt "Select Tegra processor family for target system" - config ARCH_TEGRA_2x_SOC - bool "Tegra 2 family" + bool "Enable support for Tegra20 family" select CPU_V7 select ARM_GIC select ARCH_REQUIRE_GPIOLIB @@ -17,7 +14,18 @@ config ARCH_TEGRA_2x_SOC Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller -endchoice +config ARCH_TEGRA_3x_SOC + bool "Enable support for Tegra30 family" + select CPU_V7 + select ARM_GIC + select ARCH_REQUIRE_GPIOLIB + select USB_ARCH_HAS_EHCI if USB_SUPPORT + select USB_ULPI if USB_SUPPORT + select USB_ULPI_VIEWPORT if USB_SUPPORT + select USE_OF + help + Support for NVIDIA Tegra T30 processor family, based on the + ARM CortexA9MP CPU and the ARM PL310 L2 cache controller config TEGRA_PCI bool "PCI Express support" diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index 15ee974..486b473 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -125,6 +125,9 @@ static struct { #ifdef CONFIG_ARCH_TEGRA_2x_SOC { "nvidia,tegra20", tegra20_init_early }, #endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + { "nvidia,tegra30", tegra30_init_early }, +#endif }; static void __init tegra_init_early(void) diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 355f488..f508cbb 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -26,6 +26,9 @@ #ifdef CONFIG_ARCH_TEGRA_2x_SOC void __init tegra20_init_early(void); #endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +void __init tegra30_init_early(void); +#endif void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_init_clock(void); diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 3ad1ca3..06f34ec 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -98,3 +98,10 @@ void __init tegra20_init_early(void) tegra_common_init(); } #endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +void __init tegra30_init_early(void) +{ + tegra_init_cache(0x441, 0x551); + tegra_common_init(); +} +#endif diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h index 73265af..a2146cd 100644 --- a/arch/arm/mach-tegra/include/mach/irqs.h +++ b/arch/arm/mach-tegra/include/mach/irqs.h @@ -25,7 +25,6 @@ #define IRQ_LOCALTIMER 29 -#ifdef CONFIG_ARCH_TEGRA_2x_SOC /* Primary Interrupt Controller */ #define INT_PRI_BASE (INT_GIC_BASE + 32) #define INT_TMR1 (INT_PRI_BASE + 0) @@ -178,6 +177,5 @@ #define NR_BOARD_IRQS 32 #define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) -#endif #endif -- 1.7.7.rc0.72.g4b5ea.dirty ^ permalink raw reply related [flat|nested] 23+ messages in thread
[parent not found: <1321010541-31337-10-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* RE: [PATCH v4 09/10] arm/tegra: implement support for tegra30 [not found] ` <1321010541-31337-10-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2011-11-11 22:02 ` Stephen Warren 0 siblings, 0 replies; 23+ messages in thread From: Stephen Warren @ 2011-11-11 22:02 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Peter De Schrijver wrote at Friday, November 11, 2011 4:22 AM: > Add support for tegra30 SoC. This includes a device tree compatible type for > this SoC ("nvidia,tegra30") and adds L2 cache initialization for this new SoC. > The clock framework is still missing, which prevents most drivers from working. > The basic IRQs are the same, so remove the dependency on > CONFIG_ARCH_TEGRA_2x_SOC. > diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h > #ifdef CONFIG_ARCH_TEGRA_2x_SOC > void __init tegra20_init_early(void); > #endif > +#ifdef CONFIG_ARCH_TEGRA_3x_SOC > +void __init tegra30_init_early(void); > +#endif Do we need to ifdef the prototypes? Same comment for Tegra30 here and Tegra20 in the earlier patch. -- nvpublic ^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 00/10] Add support for tegra30 and cardhu 2011-11-11 11:22 [PATCH v4 00/10] Add support for tegra30 and cardhu Peter De Schrijver ` (6 preceding siblings ...) 2011-11-11 11:22 ` [PATCH v4 09/10] arm/tegra: implement support for tegra30 Peter De Schrijver @ 2011-11-11 21:40 ` Stephen Warren 7 siblings, 0 replies; 23+ messages in thread From: Stephen Warren @ 2011-11-11 21:40 UTC (permalink / raw) To: Peter De Schrijver Cc: Russell King, Colin Cross, Olof Johansson, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Peter De Schrijver wrote at Friday, November 11, 2011 4:22 AM: > This patchset adds support for the tegra30 SoC and the cardhu development > board. Tested-by: Stephen Warren <swarren@nvidia.com> Tested: Tegra20-only build, Tegra30-only build, Tegra20+Tegra30 build. Booting on Tegra30/Cardhu: Tegra30-only build, Tegra20+Tegra30 build. Booting on Tegra20/Seaboard, using DT and board files. All testing based on next-20111111, plus Will Deacon's 3 reset patches that this relies on. I haven't actually looked at the patches yet. -- nvpublic ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2011-11-14 16:49 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
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2011-11-11 11:22 [PATCH v4 00/10] Add support for tegra30 and cardhu Peter De Schrijver
2011-11-11 11:22 ` [PATCH v4 01/10] arm/tegra: initial device tree for tegra30 Peter De Schrijver
[not found] ` <1321010541-31337-2-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2011-11-12 3:26 ` Rob Herring
[not found] ` <4EBDE766.5080505-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-14 15:25 ` Peter De Schrijver
[not found] ` <20111114152518.GJ19069-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2011-11-14 15:41 ` Rob Herring
[not found] ` <4EC13699.5030205-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-14 16:06 ` Peter De Schrijver
[not found] ` <20111114160633.GK19069-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2011-11-14 16:20 ` Stephen Warren
[not found] ` <74CDBE0F657A3D45AFBB94109FB122FF1740805A80-C7FfzLzN0UxDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
2011-11-14 16:49 ` Rob Herring
2011-11-11 11:22 ` [PATCH v4 02/10] arm/tegra: cleanup tegra20 support Peter De Schrijver
2011-11-11 11:22 ` [PATCH v4 04/10] arm/tegra: prepare early init for multiple tegra variants Peter De Schrijver
[not found] ` <1321010541-31337-5-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2011-11-11 11:45 ` Jamie Iles
2011-11-11 21:54 ` Stephen Warren
2011-11-11 21:53 ` Stephen Warren
[not found] ` <1321010541-31337-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2011-11-11 11:22 ` [PATCH v4 03/10] arm/tegra: prepare clock code " Peter De Schrijver
2011-11-11 11:22 ` [PATCH v4 05/10] arm/tegra: rename tegra20 pinmux files Peter De Schrijver
2011-11-11 11:22 ` [PATCH v4 08/10] arm/tegra: pinmux tables and definitions for tegra30 Peter De Schrijver
2011-11-11 11:22 ` [PATCH v4 10/10] arm/tegra: add support for tegra30 based board cardhu Peter De Schrijver
2011-11-11 11:22 ` [PATCH v4 06/10] arm/tegra: prepare pinmux code for multiple tegra variants Peter De Schrijver
[not found] ` <1321010541-31337-7-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2011-11-11 22:00 ` Stephen Warren
2011-11-11 11:22 ` [PATCH v4 07/10] arm/tegra: add new fields to struct tegra_pingroup_desc Peter De Schrijver
2011-11-11 11:22 ` [PATCH v4 09/10] arm/tegra: implement support for tegra30 Peter De Schrijver
[not found] ` <1321010541-31337-10-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2011-11-11 22:02 ` Stephen Warren
2011-11-11 21:40 ` [PATCH v4 00/10] Add support for tegra30 and cardhu Stephen Warren
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