[PATCH v6 05/20] tegra: fdt: Add Tegra2x device tree file from kernel

[PATCH v6 05/20] tegra: fdt: Add Tegra2x device tree file from kernel

[Simon Glass]

This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

config.mk is updated to provide this file to boards through the
built-in mechanism:

/include/ ARCH_CPU_DTS

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/arm/cpu/armv7/tegra2/config.mk |    2 +
 arch/arm/dts/tegra20.dtsi           |  168 +++++++++++++++++++++++++++++++++++
 2 files changed, 170 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/tegra20.dtsi

diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk
index 2303dba..fe9ef5b 100644
--- a/arch/arm/cpu/armv7/tegra2/config.mk
+++ b/arch/arm/cpu/armv7/tegra2/config.mk
@@ -31,3 +31,5 @@ CFLAGS_arch/arm/lib/board.o += -march=armv4t
 endif
 
 USE_PRIVATE_LIBGCC = yes
+
+CONFIG_ARCH_DEVICE_TREE := tegra20
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
new file mode 100644
index 0000000..a9a98ea
--- /dev/null
+++ b/arch/arm/dts/tegra20.dtsi
@@ -0,0 +1,168 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra20";
+	interrupt-parent = <&intc>;
+
+	intc: interrupt-controller@50041000 {
+		compatible = "nvidia,tegra20-gic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = < 0x50041000 0x1000 >,
+		      < 0x50040100 0x0100 >;
+	};
+
+	i2c@7000c000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C000 0x100>;
+		interrupts = < 70 >;
+	};
+
+	i2c@7000c400 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C400 0x100>;
+		interrupts = < 116 >;
+	};
+
+	i2c@7000c500 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C500 0x100>;
+		interrupts = < 124 >;
+	};
+
+	i2c@7000d000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000D000 0x200>;
+		interrupts = < 85 >;
+	};
+
+	i2s@70002800 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2s";
+		reg = <0x70002800 0x200>;
+		interrupts = < 45 >;
+		dma-channel = < 2 >;
+	};
+
+	i2s@70002a00 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2s";
+		reg = <0x70002a00 0x200>;
+		interrupts = < 35 >;
+		dma-channel = < 1 >;
+	};
+
+	das@70000c00 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-das";
+		reg = <0x70000c00 0x80>;
+	};
+
+	gpio: gpio@6000d000 {
+		compatible = "nvidia,tegra20-gpio";
+		reg = < 0x6000d000 0x1000 >;
+		interrupts = < 64 65 66 67 87 119 121 >;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	pinmux: pinmux@70000000 {
+		compatible = "nvidia,tegra20-pinmux";
+		reg = < 0x70000014 0x10    /* Tri-state registers */
+			0x70000080 0x20    /* Mux registers */
+			0x700000a0 0x14    /* Pull-up/down registers */
+			0x70000868 0xa8 >; /* Pad control registers */
+	};
+
+	serial@70006000 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006000 0x40>;
+		reg-shift = <2>;
+		interrupts = < 68 >;
+	};
+
+	serial@70006040 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006040 0x40>;
+		reg-shift = <2>;
+		interrupts = < 69 >;
+	};
+
+	serial@70006200 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006200 0x100>;
+		reg-shift = <2>;
+		interrupts = < 78 >;
+	};
+
+	serial@70006300 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006300 0x100>;
+		reg-shift = <2>;
+		interrupts = < 122 >;
+	};
+
+	serial@70006400 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006400 0x100>;
+		reg-shift = <2>;
+		interrupts = < 123 >;
+	};
+
+	sdhci@c8000000 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000000 0x200>;
+		interrupts = < 46 >;
+	};
+
+	sdhci@c8000200 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000200 0x200>;
+		interrupts = < 47 >;
+	};
+
+	sdhci@c8000400 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000400 0x200>;
+		interrupts = < 51 >;
+	};
+
+	sdhci@c8000600 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000600 0x200>;
+		interrupts = < 63 >;
+	};
+
+	usb@c5000000 {
+		compatible = "nvidia,tegra20-ehci", "usb-ehci";
+		reg = <0xc5000000 0x4000>;
+		interrupts = < 52 >;
+		phy_type = "utmi";
+	};
+
+	usb@c5004000 {
+		compatible = "nvidia,tegra20-ehci", "usb-ehci";
+		reg = <0xc5004000 0x4000>;
+		interrupts = < 53 >;
+		phy_type = "ulpi";
+	};
+
+	usb@c5008000 {
+		compatible = "nvidia,tegra20-ehci", "usb-ehci";
+		reg = <0xc5008000 0x4000>;
+		interrupts = < 129 >;
+		phy_type = "utmi";
+	};
+
+};
-- 
1.7.7.3

[PATCH v6 06/20] tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel

[Simon Glass]

This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---

 board/nvidia/dts/tegra2-seaboard.dts |   36 ++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)
 create mode 100644 board/nvidia/dts/tegra2-seaboard.dts

diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
new file mode 100644
index 0000000..dde5d03
--- /dev/null
+++ b/board/nvidia/dts/tegra2-seaboard.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Seaboard";
+	compatible = "nvidia,seaboard", "nvidia,tegra20";
+
+	chosen {
+		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = < 0x00000000 0x40000000 >;
+	};
+
+	serial@70006300 {
+		clock-frequency = < 216000000 >;
+	};
+
+	sdhci@c8000400 {
+		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+	};
+
+	sdhci@c8000600 {
+		support-8bit;
+	};
+
+	usb@c5000000 {
+		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+	};
+};
-- 
1.7.7.3

[PATCH v6 09/20] tegra: fdt: Add additional USB binding

[Simon Glass]

This adds a property to indicate a port which can switch between host and device
mode.

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments

 doc/device-tree-bindings/usb/tegra-usb.txt |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt
index 035d63d..b7174a3 100644
--- a/doc/device-tree-bindings/usb/tegra-usb.txt
+++ b/doc/device-tree-bindings/usb/tegra-usb.txt
@@ -11,3 +11,15 @@ Required properties :
  - phy_type : Should be one of "ulpi" or "utmi".
  - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
    activated for the bus to be powered.
+
+Optional properties:
+  - dr_mode : dual role mode. Indicates the working mode for
+   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
+   or "otg".  Default to "host" if not defined for backward compatibility.
+      host means this is a host controller
+      peripheral means it is device controller
+      otg means it can operate as either ("on the go")
+  - nvidia,has-legacy-mode : boolean indicates whether this controller can
+    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
+    registers are accessed through the APB_MISC base address instead of
+    the USB controller.
-- 
1.7.7.3

[PATCH v6 10/20] tegra: fdt: Add clock bindings

[Simon Glass]

This adds a basic binding for the oscillator and peripheral clocks. The
second cell is the clock number, defined as the bit number within the clock
enable register if the peripheral clock.

This uses the RFC clock bindings from Grant Likely so may change later:

https://lkml.org/lkml/2011/12/12/498

It is taken from Stephen Warren's patch here:

http://patchwork.ozlabs.org/patch/141359/

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v4:
- Add clock bindings for Tegra2x

Changes in v6:
- Add clock bindings from Stephen Warren's latest patch

 arch/arm/dts/tegra20.dtsi                          |   16 ++
 .../clock/nvidia,tegra20-car.txt                   |  207 ++++++++++++++++++++
 2 files changed, 223 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/clock/nvidia,tegra20-car.txt

diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index a9a98ea..2c46e11 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -4,6 +4,22 @@
 	compatible = "nvidia,tegra20";
 	interrupt-parent = <&intc>;
 
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra20-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		osc: clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
 	intc: interrupt-controller@50041000 {
 		compatible = "nvidia,tegra20-gic";
 		interrupt-controller;
diff --git a/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt b/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt
new file mode 100644
index 0000000..5c07fca
--- /dev/null
+++ b/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt
@@ -0,0 +1,207 @@
+NVIDIA Tegra20 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be "nvidia,tegra20-car"
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+  the 32 KHz "32k_in", and the board-specific oscillator "osc".
+- #clock-cells : Should be 1.
+  In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  registers. These IDs often match those in the CAR's RST_DEVICES registers,
+  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+  this case, those clocks are assigned IDs above 95 in order to highlight
+  this issue. Implementations that interpret these clock IDs as bit values
+  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+  explicitly handle these special cases.
+
+  The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+  above.
+
+  0	cpu
+  1	unassigned
+  2	unassigned
+  3	ac97
+  4	rtc
+  5	tmr
+  6	uart1
+  7	unassigned	(register bit affects uart2 and vfir)
+  8	gpio
+  9	sdmmc2
+  10	unassigned	(register bit affects spdif_in and spdif_out)
+  11	i2s1
+  12	i2c1
+  13	ndflash
+  14	sdmmc1
+  15	sdmmc4
+  16	twc
+  17	pwm
+  18	i2s2
+  19	epp
+  20	unassigned	(register bit affects vi and vi_sensor)
+  21	2d
+  22	usbd
+  23	isp
+  24	3d
+  25	ide
+  26	disp2
+  27	disp1
+  28	host1x
+  29	vcp
+  30	unassigned
+  31	cache2
+
+  32	mem
+  33	ahbdma
+  34	apbdma
+  35	unassigned
+  36	kbc
+  37	stat_mon
+  38	pmc
+  39	fuse
+  40	kfuse
+  41	sbc1
+  42	snor
+  43	spi1
+  44	sbc2
+  45	xio
+  46	sbc3
+  47	dvc
+  48	dsi
+  49	unassigned	(register bit affects tvo and cve)
+  50	mipi
+  51	hdmi
+  52	csi
+  53	tvdac
+  54	i2c2
+  55	uart3
+  56	unassigned
+  57	emc
+  58	usb2
+  59	usb3
+  60	mpe
+  61	vde
+  62	bsea
+  63	bsev
+
+  64	speedo
+  65	uart4
+  66	uart5
+  67	i2c3
+  68	sbc4
+  69	sdmmc3
+  70	pcie
+  71	owr
+  72	afi
+  73	csite
+  74	unassigned
+  75	avpucq
+  76	la
+  77	unassigned
+  78	unassigned
+  79	unassigned
+  80	unassigned
+  81	unassigned
+  82	unassigned
+  83	unassigned
+  84	irama
+  85	iramb
+  86	iramc
+  87	iramd
+  88	cram2
+  89	audio_2x	a/k/a audio_2x_sync_clk
+  90	clk_d
+  91	unassigned
+  92	sus
+  93	cdev1
+  94	cdev2
+  95	unassigned
+
+  96	uart2
+  97	vfir
+  98	spdif_in
+  99	spdif_out
+  100	vi
+  101	vi_sensor
+  102	tvo
+  103	cve
+  104	osc
+  105	clk_32k		a/k/a clk_s
+  106	clk_m
+  107	sclk
+  108	cclk
+  109	hclk
+  110	pclk
+  111	blink
+  112	pll_a
+  113	pll_a_out0
+  114	pll_c
+  115	pll_c_out1
+  116	pll_d
+  117	pll_d_out0
+  118	pll_e
+  119	pll_m
+  120	pll_m_out1
+  121	pll_p
+  122	pll_p_out1
+  123	pll_p_out2
+  124	pll_p_out3
+  125	pll_p_out4
+  126	pll_s
+  127	pll_u
+  128	pll_x
+  129	cop		a/k/a avp
+  130	audio		a/k/a audio_sync_clk
+
+Example SoC include file:
+
+/ {
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra20-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	usb@c5004000 {
+		clocks = <&tegra_car 58>; /* usb2 */
+	};
+};
+
+Example board file:
+
+/ {
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		osc: clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12000000>;
+		};
+	};
+
+	i2c@7000d000 {
+		pmic@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+
+			clk_32k: clock {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <32768>;
+			};
+		};
+	};
+
+	&tegra_car {
+		clocks = <&clk_32k> <&osc>;
+	};
+};
-- 
1.7.7.3

[PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Simon Glass]

Add the definition of the oscillator clock frequency.

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v6:
- Add new patch to bring in clock bindings to seaboard

 board/nvidia/dts/tegra2-seaboard.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
index dde5d03..87f58fb 100644
--- a/board/nvidia/dts/tegra2-seaboard.dts
+++ b/board/nvidia/dts/tegra2-seaboard.dts
@@ -16,6 +16,16 @@
 		reg = < 0x00000000 0x40000000 >;
 	};
 
+	clocks {
+		osc {
+			clock-frequency = <12000000>;
+		};
+	};
+
+	clock@60006000 {
+		clocks = <&osc>;
+	};
+
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
-- 
1.7.7.3

[PATCH v6 12/20] tegra: usb: fdt: Add additional device tree definitions for USB ports

[Simon Glass]

This adds clock references to the USB part of the device tree for U-Boot,
and marks USB1 as supporting legacy mode (which we disable in the driver).

The USB timing information may vary between boards sometimes, but for
now we hard-code it in C. This is because all current T2x boards use
the same values, we will deal with T3x later and we first need to agree
on the format for this timing information in the fdt and may in fact
decide that it has no place there.

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments
- Change device tree comment style from // to /* */

Changes in v6:
- Remove dr_mode properties from SOC .dtsi file and move to boards

 arch/arm/dts/tegra20.dtsi |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 2c46e11..d6bc9f1 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -165,6 +165,8 @@
 		reg = <0xc5000000 0x4000>;
 		interrupts = < 52 >;
 		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		nvidia,has-legacy-mode;
 	};
 
 	usb@c5004000 {
@@ -172,6 +174,7 @@
 		reg = <0xc5004000 0x4000>;
 		interrupts = < 53 >;
 		phy_type = "ulpi";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
 	};
 
 	usb@c5008000 {
@@ -179,6 +182,7 @@
 		reg = <0xc5008000 0x4000>;
 		interrupts = < 129 >;
 		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
 	};
 
 };
-- 
1.7.7.3

[PATCH v6 13/20] tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard

[Simon Glass]

We set up two USB ports, one of which can be host or device.
For some reason the kernel version does enable both ports.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Remove 0x from fdt aliases
- Use "okay" instead of "ok" for fdt node status

Changes in v3:
- Disable USB2 which is not used on Seaboard
- Fix device tree indenting with tabs instead of spaces
- Remove "okay" from nodes since this is the default anyway

Changes in v5:
- Remove support-host-mode property

Changes in v6:
- Remove dr_mode properties from SOC .dtsi file and move to boards

 board/nvidia/dts/tegra2-seaboard.dts |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
index 87f58fb..4fbb252 100644
--- a/board/nvidia/dts/tegra2-seaboard.dts
+++ b/board/nvidia/dts/tegra2-seaboard.dts
@@ -11,6 +11,12 @@
 		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
 	};
 
+	aliases {
+		/* This defines the order of our USB ports */
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
+	};
+
 	memory {
 		device_type = "memory";
 		reg = < 0x00000000 0x40000000 >;
@@ -42,5 +48,10 @@
 
 	usb@c5000000 {
 		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		dr_mode = "otg";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
 	};
 };
-- 
1.7.7.3

[PATCH v6 15/20] tegra: fdt: Add function to return peripheral/clock ID

[Simon Glass]

A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).

Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v4:
- Add fdtdec function to return peripheral ID

Changes in v6:
- Move peripheral decode function into Tegra's clock.c

 arch/arm/cpu/armv7/tegra2/clock.c        |   19 +++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/clock.h |   13 +++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c
index 11d2346..ffbfc28 100644
--- a/arch/arm/cpu/armv7/tegra2/clock.c
+++ b/arch/arm/cpu/armv7/tegra2/clock.c
@@ -28,6 +28,7 @@
 #include <asm/arch/tegra2.h>
 #include <common.h>
 #include <div64.h>
+#include <fdtdec.h>
 
 /*
  * This is our record of the current clock rate of each clock. We don't
@@ -918,6 +919,24 @@ void clock_ll_start_uart(enum periph_id periph_id)
 	reset_set_enable(periph_id, 0);
 }
 
+
+int clock_decode_periph_id(const void *blob, int node)
+{
+	enum periph_id id;
+	int err, valid;
+	u32 cell[2];
+
+	err = fdtdec_get_int_array(blob, node, "clocks", cell,
+				   ARRAY_SIZE(cell));
+	if (err)
+		return -1;
+	id = cell[1];
+
+	valid = clock_periph_id_isvalid(id);
+	assert(valid);
+	return valid ? id : PERIPH_ID_NONE;
+}
+
 int clock_verify(void)
 {
 	struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h
index 080ef18..6b12c76 100644
--- a/arch/arm/include/asm/arch-tegra2/clock.h
+++ b/arch/arm/include/asm/arch-tegra2/clock.h
@@ -177,6 +177,7 @@ enum periph_id {
 	PERIPH_ID_CRAM2,
 
 	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
 };
 
 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
@@ -355,6 +356,18 @@ unsigned clock_get_rate(enum clock_id clkid);
  */
 void clock_ll_start_uart(enum periph_id periph_id);
 
+/**
+ * Decode a peripheral ID from a device tree node.
+ *
+ * This works by looking up the peripheral's 'clocks' node and reading out
+ * the second cell, which is the clock number / peripheral ID.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node to look at
+ * @return peripheral ID, or PERIPH_ID_NONE if none
+ */
+enum periph_id clock_decode_periph_id(const void *blob, int node);
+
 /*
  * Checks that clocks are valid and prints a warning if not
  *
-- 
1.7.7.3

[PATCH v6 16/20] tegra: usb: Add support for Tegra USB peripheral

[Simon Glass]

This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.

Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:

        aliases {
		/* This defines the order of our USB ports */
                usb0 = "/usb@0xc5008000";
                usb1 = "/usb@0xc5000000";
        };

drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux-SYUVB/VFmdasTnJN9+BGXg@public.gmane.org>
Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v2:
- Decode USB VBUS GPIO from the fdt
- Decode phy type differently (to match new kernel fdt)
- Improve debug() printouts in case of failure to init USB
- Remove non-fdt operation of USB, since it is not needed
- Rename params to timing
- Rename tegra20-usb to tegra20-ehcui (to match new kernel fdt)
- Store entire fdt config in port list, not just register pointer

Changes in v3:
- Remove usbparams properties from fdt and moved them to C code

Changes in v4:
- Use peripheral clock node to obtain peripheral ID
- Use updated fdtdec alias functiona to get USB aliases

Changes in v5:
- Add additional debugging to report active USB ports
- Allow any port to operate in otg mode
- Correct PTS_MASK value to be unsigned
- Implement new device tree properties
- Remove checking of peripheral ID and try to use only device tree
- Report error if phy clock does not start up

Changes in v6:
- Use updated clock_decode_periph_id() function

 arch/arm/cpu/armv7/tegra2/Makefile        |    4 +-
 arch/arm/cpu/armv7/tegra2/usb.c           |  460 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/tegra2.h |    2 +
 arch/arm/include/asm/arch-tegra2/usb.h    |  252 ++++++++++++++++
 drivers/usb/host/Makefile                 |    1 +
 drivers/usb/host/ehci-tegra.c             |   62 ++++
 include/fdtdec.h                          |    1 +
 lib/fdtdec.c                              |    1 +
 8 files changed, 782 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h
 create mode 100644 drivers/usb/host/ehci-tegra.c

diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile
index f668a81..e9ac6c9 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-y	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 
diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c
new file mode 100644
index 0000000..c80de7f
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/usb.c
@@ -0,0 +1,460 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/usb.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+
+enum {
+	USB_PORTS_MAX	= 4,			/* Maximum ports we allow */
+};
+
+/* Parameters we need for USB */
+enum {
+	PARAM_DIVN,                     /* PLL FEEDBACK DIVIDer */
+	PARAM_DIVM,                     /* PLL INPUT DIVIDER */
+	PARAM_DIVP,                     /* POST DIVIDER (2^N) */
+	PARAM_CPCON,                    /* BASE PLLC CHARGE Pump setup ctrl */
+	PARAM_LFCON,                    /* BASE PLLC LOOP FILter setup ctrl */
+	PARAM_ENABLE_DELAY_COUNT,       /* PLL-U Enable Delay Count */
+	PARAM_STABLE_COUNT,             /* PLL-U STABLE count */
+	PARAM_ACTIVE_DELAY_COUNT,       /* PLL-U Active delay count */
+	PARAM_XTAL_FREQ_COUNT,          /* PLL-U XTAL frequency count */
+	PARAM_DEBOUNCE_A_TIME,          /* 10MS DELAY for BIAS_DEBOUNCE_A */
+	PARAM_BIAS_TIME,                /* 20US DELAY AFter bias cell op */
+
+	PARAM_COUNT
+};
+
+/* Possible port types (dual role mode) */
+enum dr_mode {
+	DR_MODE_NONE = 0,
+	DR_MODE_HOST,		/* supports host operation */
+	DR_MODE_DEVICE,		/* supports device operation */
+	DR_MODE_OTG,		/* supports both */
+};
+
+/* Information about a USB port */
+struct fdt_usb {
+	struct usb_ctlr *reg;	/* address of registers in physical memory */
+	unsigned utmi:1;	/* 1 if port has external tranceiver, else 0 */
+	unsigned enabled:1;	/* 1 to enable, 0 to disable */
+	unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
+	enum dr_mode dr_mode;	/* dual role mode */
+	enum periph_id periph_id;/* peripheral id */
+	struct fdt_gpio_state vbus_gpio;	/* GPIO for vbus enable */
+};
+
+static struct fdt_usb port[USB_PORTS_MAX];	/* List of valid USB ports */
+static unsigned port_count;			/* Number of available ports */
+static int port_current;			/* Current port (-1 = none) */
+
+/*
+ * This table has USB timing parameters for each Oscillator frequency we
+ * support. There are four sets of values:
+ *
+ * 1. PLLU configuration information (reference clock is osc/clk_m and
+ * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
+ *
+ *  Reference frequency     13.0MHz      19.2MHz      12.0MHz      26.0MHz
+ *  ----------------------------------------------------------------------
+ *      DIVN                960 (0x3c0)  200 (0c8)    960 (3c0h)   960 (3c0)
+ *      DIVM                13 (0d)      4 (04)       12 (0c)      26 (1a)
+ * Filter frequency (MHz)   1            4.8          6            2
+ * CPCON                    1100b        0011b        1100b        1100b
+ * LFCON0                   0            0            0            0
+ *
+ * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
+ *
+ * Reference frequency     13.0MHz         19.2MHz         12.0MHz     26.0MHz
+ * ---------------------------------------------------------------------------
+ * PLLU_ENABLE_DLY_COUNT   02 (0x02)       03 (03)         02 (02)     04 (04)
+ * PLLU_STABLE_COUNT       51 (33)         75 (4B)         47 (2F)    102 (66)
+ * PLL_ACTIVE_DLY_COUNT    05 (05)         06 (06)         04 (04)     09 (09)
+ * XTAL_FREQ_COUNT        127 (7F)        187 (BB)        118 (76)    254 (FE)
+ *
+ * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
+ * SessEnd. Each of these signals have their own debouncer and for each of
+ * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
+ * BIAS_DEBOUNCE_B).
+ *
+ * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
+ *    0xffff -> No debouncing at all
+ *    <n> ms = <n> *1000 / (1/19.2MHz) / 4
+ *
+ * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
+ * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4  = 4800 = 0x12c0
+ *
+ * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
+ * values, so we can keep those to default.
+ *
+ * 4. The 20 microsecond delay after bias cell operation.
+ */
+static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
+	{ 0x3C0, 0x0D, 0x00, 0xC,   0,  0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
+	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
+	{ 0x3C0, 0x0C, 0x00, 0xC,   0,  0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
+	{ 0x3C0, 0x1A, 0x00, 0xC,   0,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+};
+
+/* UTMIP Idle Wait Delay */
+static const u8 utmip_idle_wait_delay = 17;
+
+/* UTMIP Elastic limit */
+static const u8 utmip_elastic_limit = 16;
+
+/* UTMIP High Speed Sync Start Delay */
+static const u8 utmip_hs_sync_start_delay = 9;
+
+/* Put the port into host mode (this only works for OTG ports) */
+static void set_host_mode(struct fdt_usb *config)
+{
+	if (config->dr_mode == DR_MODE_OTG) {
+		/* Check whether remote host from USB1 is driving VBus */
+		if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)
+			return;
+
+		/*
+		 * If not driving, we set the GPIO to enable VBUS. We assume
+		 * that the pinmux is set up correctly for this.
+		 */
+		if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+			fdtdec_setup_gpio(&config->vbus_gpio);
+			gpio_direction_output(config->vbus_gpio.gpio, 1);
+			debug("set_host_mode: GPIO %d high\n",
+			      config->vbus_gpio.gpio);
+		}
+	}
+}
+
+void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
+{
+	/* Reset the USB controller with 2us delay */
+	reset_periph(config->periph_id, 2);
+
+	/*
+	 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
+	 * base address
+	 */
+	if (config->has_legacy_mode)
+		setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
+
+	/* Put UTMIP1/3 in reset */
+	setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+	/* Enable the UTMIP PHY */
+	if (config->utmi)
+		setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
+
+	/*
+	 * TODO: where do we take the USB1 out of reset? The old code would
+	 * take USB3 out of reset, but not USB1. This code doesn't do either.
+	 */
+}
+
+/* set up the USB controller with the parameters provided */
+static int init_usb_controller(struct fdt_usb *config,
+				struct usb_ctlr *usbctlr, const u32 timing[])
+{
+	u32 val;
+	int loop_count;
+
+	clock_enable(config->periph_id);
+
+	/* Reset the usb controller */
+	usbf_reset_controller(config, usbctlr);
+
+	/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
+	clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+	/* Follow the crystal clock disable by >100ns delay */
+	udelay(1);
+
+	/*
+	 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
+	 * mux must be switched to actually use a_sess_vld threshold.
+	 */
+	if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+		clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
+			VBUS_SENSE_CTL_MASK,
+			VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
+	}
+
+	/*
+	 * PLL Delay CONFIGURATION settings. The following parameters control
+	 * the bring up of the plls.
+	 */
+	val = readl(&usbctlr->utmip_misc_cfg1);
+	clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+		timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+		timing[PARAM_ACTIVE_DELAY_COUNT] <<
+			UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+	writel(val, &usbctlr->utmip_misc_cfg1);
+
+	/* Set PLL enable delay count and crystal frequency count */
+	val = readl(&usbctlr->utmip_pll_cfg1);
+	clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+		timing[PARAM_ENABLE_DELAY_COUNT] <<
+			UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+		timing[PARAM_XTAL_FREQ_COUNT] <<
+			UTMIP_XTAL_FREQ_COUNT_SHIFT);
+	writel(val, &usbctlr->utmip_pll_cfg1);
+
+	/* Setting the tracking length time */
+	clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
+		UTMIP_BIAS_PDTRK_COUNT_MASK,
+		timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
+
+	/* Program debounce time for VBUS to become valid */
+	clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
+		UTMIP_DEBOUNCE_CFG0_MASK,
+		timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
+
+	setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
+
+	/* Disable battery charge enabling bit */
+	setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
+
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
+	setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
+
+	/*
+	 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
+	 * Setting these fields, together with default values of the
+	 * other fields, results in programming the registers below as
+	 * follows:
+	 *         UTMIP_HSRX_CFG0 = 0x9168c000
+	 *         UTMIP_HSRX_CFG1 = 0x13
+	 */
+
+	/* Set PLL enable delay count and Crystal frequency count */
+	val = readl(&usbctlr->utmip_hsrx_cfg0);
+	clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
+		utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
+		utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
+	writel(val, &usbctlr->utmip_hsrx_cfg0);
+
+	/* Configure the UTMIP_HS_SYNC_START_DLY */
+	clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
+		UTMIP_HS_SYNC_START_DLY_MASK,
+		utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
+
+	/* Preceed the crystal clock disable by >100ns delay. */
+	udelay(1);
+
+	/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
+	setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+	/* Finished the per-controller init. */
+
+	/* De-assert UTMIP_RESET to bring out of reset. */
+	clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+	/* Wait for the phy clock to become valid in 100 ms */
+	for (loop_count = 100000; loop_count != 0; loop_count--) {
+		if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
+			break;
+		udelay(1);
+	}
+	if (loop_count == 100000)
+		return -1;
+
+	return 0;
+}
+
+static void power_up_port(struct usb_ctlr *usbctlr)
+{
+	/* Deassert power down state */
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
+		UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
+		UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+}
+
+static void config_clock(const u32 timing[])
+{
+	clock_start_pll(CLOCK_ID_USB,
+		timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
+		timing[PARAM_CPCON], timing[PARAM_LFCON]);
+}
+
+/**
+ * Add a new USB port to the list of available ports.
+ *
+ * @param config	USB port configuration
+ * @return 0 if ok, -1 if error (too many ports)
+ */
+static int add_port(struct fdt_usb *config, const u32 timing[])
+{
+	struct usb_ctlr *usbctlr = config->reg;
+
+	if (port_count == USB_PORTS_MAX) {
+		debug("tegrausb: Cannot register more than %d ports\n",
+		      USB_PORTS_MAX);
+		return -1;
+	}
+	if (init_usb_controller(config, usbctlr, timing)) {
+		debug("tegrausb: Cannot init port\n");
+		return -1;
+	}
+	if (config->utmi) {
+		/* Disable ICUSB FS/LS transceiver */
+		clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
+
+		/* Select UTMI parallel interface */
+		clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+				PTS_UTMI << PTS_SHIFT);
+		clrbits_le32(&usbctlr->port_sc1, STS);
+		power_up_port(usbctlr);
+	}
+	port[port_count++] = *config;
+
+	return 0;
+}
+
+int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor)
+{
+	struct usb_ctlr *usbctlr;
+
+	if (portnum >= port_count)
+		return -1;
+	tegrausb_stop_port();
+	set_host_mode(&port[portnum]);
+
+	usbctlr = port[portnum].reg;
+	*hccr = (u32)&usbctlr->cap_length;
+	*hcor = (u32)&usbctlr->usb_cmd;
+	port_current = portnum;
+	return 0;
+}
+
+int tegrausb_stop_port(void)
+{
+	struct usb_ctlr *usbctlr;
+
+	if (port_current == -1)
+		return -1;
+
+	usbctlr = port[port_current].reg;
+
+	/* Stop controller */
+	writel(0, &usbctlr->usb_cmd);
+	udelay(1000);
+
+	/* Initiate controller reset */
+	writel(2, &usbctlr->usb_cmd);
+	udelay(1000);
+	port_current = -1;
+	return 0;
+}
+
+int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
+		   struct fdt_usb *config)
+{
+	const char *phy, *mode;
+
+	config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	mode = fdt_getprop(blob, node, "dr_mode", NULL);
+	if (mode) {
+		if (0 == strcmp(mode, "host"))
+			config->dr_mode = DR_MODE_HOST;
+		else if (0 == strcmp(mode, "peripheral"))
+			config->dr_mode = DR_MODE_DEVICE;
+		else if (0 == strcmp(mode, "otg"))
+			config->dr_mode = DR_MODE_OTG;
+		else {
+			debug("%s: Cannot decode dr_mode '%s'\n", __func__,
+			      mode);
+			return -FDT_ERR_NOTFOUND;
+		}
+	} else {
+		config->dr_mode = DR_MODE_HOST;
+	}
+
+	phy = fdt_getprop(blob, node, "phy_type", NULL);
+	config->utmi = phy && 0 == strcmp("utmi", phy);
+	config->enabled = fdtdec_get_is_enabled(blob, node);
+	config->has_legacy_mode = fdtdec_get_bool(blob, node,
+						  "nvidia,has-legacy-mode");
+	config->periph_id = clock_decode_periph_id(blob, node);
+	if (config->periph_id == PERIPH_ID_NONE) {
+		debug("%s: Missing/invalid peripheral ID\n", __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+	fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
+	debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, "
+	      "dr_mode=%d\n", config->enabled, config->has_legacy_mode,
+	      config->utmi, config->periph_id, config->vbus_gpio.gpio,
+	      config->dr_mode);
+
+	return 0;
+}
+
+int board_usb_init(const void *blob)
+{
+	struct fdt_usb config;
+	unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
+	enum clock_osc_freq freq;
+	int node_list[USB_PORTS_MAX];
+	int node, count, i;
+
+	/* Set up the USB clocks correctly based on our oscillator frequency */
+	freq = clock_get_osc_freq();
+	config_clock(usb_pll[freq]);
+
+	/* count may return <0 on error */
+	count = fdtdec_find_aliases_for_id(blob, "usb",
+			COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
+	for (i = 0; i < count; i++) {
+		debug("USB %d: ", i);
+		node = node_list[i];
+		if (!node)
+			continue;
+		if (fdt_decode_usb(blob, node, osc_freq, &config)) {
+			debug("Cannot decode USB node %s\n",
+			      fdt_get_name(blob, node, NULL));
+			return -1;
+		}
+
+		if (add_port(&config, usb_pll[freq]))
+			return -1;
+		set_host_mode(&config);
+	}
+	port_current = -1;
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 8941443..baae2eb 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -41,6 +41,8 @@
 #define TEGRA2_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
 #define NV_PA_PMC_BASE		0x7000E400
 #define NV_PA_CSITE_BASE	0x70040000
+#define TEGRA_USB1_BASE		0xC5000000
+#define TEGRA_USB3_BASE		0xC5008000
 
 #define TEGRA2_SDRC_CS0		NV_PA_SDRAM_BASE
 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC
diff --git a/arch/arm/include/asm/arch-tegra2/usb.h b/arch/arm/include/asm/arch-tegra2/usb.h
new file mode 100644
index 0000000..638033b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/usb.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_USB_H_
+#define _TEGRA_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[6];
+
+	/* 0x140 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x150 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint async_tt_sts;
+
+	/* 0x160 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;   /* is this port_sc1 on some controllers? */
+	uint icusb_ctrl;
+
+	/* 0x170 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint endpt_nak;
+	uint endpt_nak_enable;
+
+	/* 0x180 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x1a0 */
+	uint reserved9;
+	uint otgsc;
+	uint usb_mode;
+	uint endpt_setup_stat;
+
+	/* 0x1b0 */
+	uint reserved10[20];
+
+	/* 0x200 */
+	uint reserved11[0x80];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE		1
+
+#define VBUS_SENSE_CTL_SHIFT			1
+#define VBUS_SENSE_CTL_MASK			(3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP		0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP	1
+#define VBUS_SENSE_CTL_AB_SESS_VLD		2
+#define VBUS_SENSE_CTL_A_SESS_VLD		3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB			        (1 << 12)
+#define UTMIP_RESET			        (1 << 11)
+#define USB_PHY_CLK_VALID			(1 << 7)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
+#define UTMIP_PLLU_STABLE_COUNT_MASK		\
+				(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT	18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK		\
+				(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define UTMIP_PHY_XTAL_CLOCKEN			(1 << 30)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
+				(0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
+#define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK		\
+				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+#define UTMIP_DEBOUNCE_CFG0_SHIFT		0
+#define UTMIP_DEBOUNCE_CFG0_MASK		0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J			(1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG				1
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL				(1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT			15
+#define UTMIP_IDLE_WAIT_MASK			(0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT		10
+#define UTMIP_ELASTIC_LIMIT_MASK		\
+				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT		1
+#define UTMIP_HS_SYNC_START_DLY_MASK		\
+				(0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1					(1 << 3)
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define PTS_SHIFT				30
+#define PTS_MASK				(3U << PTS_SHIFT)
+#define PTS_UTMI	0
+#define PTS_RESERVED	1
+#define PTS_ULP		2
+#define PTS_ICUSB_SER	3
+
+#define STS					(1 << 29)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS			(1 << 26)
+
+
+/* Change the USB host port into host mode */
+void usb_set_host_mode(void);
+
+/* Setup USB on the board */
+int board_usb_init(const void *blob);
+
+/**
+ * Start up the given port number (ports are numbered from 0 on each board).
+ * This returns values for the appropriate hccr and hcor addresses to use for
+ * USB EHCI operations.
+ *
+ * @param portnum	port number to start
+ * @param hccr		returns start address of EHCI HCCR registers
+ * @param hcor		returns start address of EHCI HCOR registers
+ * @return 0 if ok, -1 on error (generally invalid port number)
+ */
+int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor);
+
+/**
+ * Stop the current port
+ *
+ * @return 0 if ok, -1 if no port was active
+ */
+int tegrausb_stop_port(void);
+
+#endif	/* _TEGRA_USB_H_ */
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 77e217f..a11cebb 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
new file mode 100644
index 0000000..a7e105b
--- /dev/null
+++ b/drivers/usb/host/ehci-tegra.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+#include <asm/errno.h>
+#include <asm/arch/usb.h>
+
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+	u32 our_hccr, our_hcor;
+
+	/*
+	 * Select the first port, as we don't have a way of selecting others
+	 * yet
+	 */
+	if (tegrausb_start_port(0, &our_hccr, &our_hcor))
+		return -1;
+
+	hccr = (struct ehci_hccr *)our_hccr;
+	hcor = (struct ehci_hcor *)our_hcor;
+
+	return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+	tegrausb_stop_port();
+	return 0;
+}
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 6c0a2d1..2ac8c9c 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -57,6 +57,7 @@ struct fdt_memory {
  */
 enum fdt_compat_id {
 	COMPAT_UNKNOWN,
+	COMPAT_NVIDIA_TEGRA20_USB,	/* Tegra2 USB port */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index c748cac..5f137a5 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define COMPAT(id, name) name
 static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(UNKNOWN, "<none>"),
+	COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
1.7.7.3

[PATCH v6 17/20] tegra: usb: Add USB support to nvidia boards

[Simon Glass]

This adds basic USB support for port 0. The other port is not supported
yet.

Tegra2 (SeaBoard) # usb start
(Re)start USB...
USB:   Register 10011 NbrPorts 1
USB EHCI 1.00
scanning bus for devices... 5 USB Device(s) found
       scanning bus for storage devices... 1 Storage Device(s) found
Tegra2 (SeaBoard) # ext2load usb 0:3 10000000 /boot/vmlinuz
Loading file "/boot/vmlinuz" from usb device 0:3 (ROOT-A)
2932976 bytes read

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v2:
- Add setting of pinmux for USB VBUS GPIO

Changes in v5:
- Put pinmux setting into a board-specific function

 board/nvidia/common/board.c      |   12 ++++++++++++
 board/nvidia/common/board.h      |    6 ++++++
 board/nvidia/seaboard/seaboard.c |    6 ++++++
 3 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index e8253a0..72d8630 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -33,6 +33,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/uart.h>
 #include <spi.h>
+#include <asm/arch/usb.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -50,6 +51,12 @@ int timer_init(void)
 	return 0;
 }
 
+void __pin_mux_usb(void)
+{
+}
+
+void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -69,6 +76,11 @@ int board_init(void)
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
+#ifdef CONFIG_USB_EHCI_TEGRA
+	pin_mux_usb();
+	board_usb_init(gd->fdt_blob);
+#endif
+
 	return 0;
 }
 
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h
index a638af2..09fb158 100644
--- a/board/nvidia/common/board.h
+++ b/board/nvidia/common/board.h
@@ -27,4 +27,10 @@
 void gpio_config_uart(void);
 void gpio_early_init_uart(void);
 
+/*
+ * Set up any pin muxing needed for USB (for now, since fdt doesn't support
+ * it). Boards can overwrite the default fucction which does nothing.
+ */
+void pin_mux_usb(void);
+
 #endif	/* BOARD_H */
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 9ab6825..94efb1e 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -90,3 +90,9 @@ int board_mmc_init(bd_t *bd)
 	return 0;
 }
 #endif
+
+void pin_mux_usb(void)
+{
+	/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
+	pinmux_tristate_disable(PINGRP_SLXK);
+}
-- 
1.7.7.3

[PATCH v6 18/20] tegra: usb: Add common USB defines for tegra2 boards

[Simon Glass]

All Tegra2 boards should include tegra2-common. This adds the required
USB config to that file.

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v5:
- Add CONFIG_EHCI_DCACHE which is needed for dcache operation
- Drop unused CONFIG_USB_EHCI_DATA_ALIGN option

 include/configs/tegra2-common.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index e6f385f..266d0e5 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -84,6 +84,16 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 
+/*
+ * This parameter affects a TXFILLTUNING field that controls how much data is
+ * sent to the latency fifo before it is sent to the wire. Without this
+ * parameter, the default (2) causes occasional Data Buffer Errors in OUT
+ * packets depending on the buffer address and size.
+ */
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	10
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_DCACHE
+
 /* include default commands */
 #include <config_cmd_default.h>
 
-- 
1.7.7.3

[PATCH v6 19/20] tegra: usb: Enable USB on Seaboard

[Simon Glass]

Seaboard has a top port which is USB host or device, and a side port which
is host only.

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v2:
- Remove unneeded CONFIG_TEGRA_USBx defines

 include/configs/seaboard.h |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 261f952..b6d9f7a 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -72,4 +72,11 @@
 
 #define CONFIG_ENV_SECT_SIZE    CONFIG_ENV_SIZE
 #define CONFIG_ENV_OFFSET       (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
 #endif /* __CONFIG_H */
-- 
1.7.7.3

[PATCH v6 20/20] tegra: fdt: Enable FDT support for Seaboard

[Simon Glass]

This switches Seaboard over to use FDT for run-time config instead of
CONFIG options. USB is the only user at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v3:
- Drop Tegra USB alignment patch as we will deal with this another way

Changes in v6:
- Drop fdt alignment patch as we will handle this after generic reloc

 include/configs/seaboard.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index b6d9f7a..1dc775a 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -27,6 +27,11 @@
 #include <asm/sizes.h>
 #include "tegra2-common.h"
 
+/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-seaboard
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
 /* High-level configuration options */
 #define TEGRA2_SYSMEM		"mem=384M@0M nvmem=128M@384M mem=512M@512M"
 #define V_PROMPT		"Tegra2 (SeaBoard) # "
-- 
1.7.7.3

Re: [PATCH v6 09/20] tegra: fdt: Add additional USB binding

[Stephen Warren]

On 02/27/2012 01:52 PM, Simon Glass wrote:
> This adds a property to indicate a port which can switch between host and device
> mode.
...
> diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt
...
> +Optional properties:
> +  - dr_mode : dual role mode. Indicates the working mode for
> +   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
> +   or "otg".  Default to "host" if not defined for backward compatibility.

Those last two lines need to be indented 1 extra space each so the text
lines up with "dr_mode". I assume that Tom can do this when applying the
change to save any respins etc.

-- 
nvpublic

Re: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Stephen Warren]

On 02/27/2012 01:52 PM, Simon Glass wrote:
> Add the definition of the oscillator clock frequency.

> diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts

> +	clock@60006000 {
> +		clocks = <&osc>;
> +	};

The CAR takes two clock inputs; one 32KHz clock (typically from the
PMU/PMIC) and one from the oscillator. The 32KHz one is missing here. I
guess this won't make any difference to U-Boot since it isn't using the
clock inputs in the CAR driver, but it'd be best if the .dts file
contained the correct content so it didn't act as an incorrect example.
See the example in the binding documentation for what should be there.

-- 
nvpublic

Re: [PATCH v6 15/20] tegra: fdt: Add function to return peripheral/clock ID

[Stephen Warren]

On 02/27/2012 01:52 PM, Simon Glass wrote:
> A common requirement is to find the clock ID for a peripheral. This is the
> second cell of the 'clocks' property (the first being the phandle itself).

> +int clock_decode_periph_id(const void *blob, int node)

> +	valid = clock_periph_id_isvalid(id);

clock_periph_id_isvalid() is not the correct function to use here; the
code should be checking for invalid IDs in the CAR binding, not invalid
IDs in the HW periph ID definition. They're different.

Just to be explicit, the function you need here would be:

int clkid_to_periphid(int clkid)
{
    if (clk_id > 95)
        return -1;
    switch (clk_id) {
    case 1:
    case 2:
    case 7:
    case 10:
    case 20:
    case 30:
    case 35:
    case 49:
    case 56:
    case 74:
    case 77:
    case 78:
    case 79:
    case 80:
    case 81:
    case 82:
    case 83:
    case 91:
    case 95:
        return -1;
    default:
        return clkid;
    }
}

-- 
nvpublic

Re: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Simon Glass]

Hi Stephen,

On Mon, Feb 27, 2012 at 3:29 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> On 02/27/2012 01:52 PM, Simon Glass wrote:
>> Add the definition of the oscillator clock frequency.
>
>> diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
>
>> +     clock@60006000 {
>> +             clocks = <&osc>;
>> +     };
>
> The CAR takes two clock inputs; one 32KHz clock (typically from the
> PMU/PMIC) and one from the oscillator. The 32KHz one is missing here. I
> guess this won't make any difference to U-Boot since it isn't using the
> clock inputs in the CAR driver, but it'd be best if the .dts file
> contained the correct content so it didn't act as an incorrect example.
> See the example in the binding documentation for what should be there.

Yes I saw that - but it adds an i2c binding which I don't yet have. I
add i2c in the next series.

I will add that one i2c node here.

Regards,
Simon

>
> --
> nvpublic
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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RE: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Stephen Warren]

Simon Glass wrote at Tuesday, February 28, 2012 10:21 AM:
> On Mon, Feb 27, 2012 at 3:29 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> > On 02/27/2012 01:52 PM, Simon Glass wrote:
> >> Add the definition of the oscillator clock frequency.
> >
> >> diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
> >
> >> +     clock@60006000 {
> >> +             clocks = <&osc>;
> >> +     };
> >
> > The CAR takes two clock inputs; one 32KHz clock (typically from the
> > PMU/PMIC) and one from the oscillator. The 32KHz one is missing here. I
> > guess this won't make any difference to U-Boot since it isn't using the
> > clock inputs in the CAR driver, but it'd be best if the .dts file
> > contained the correct content so it didn't act as an incorrect example.
> > See the example in the binding documentation for what should be there.
> 
> Yes I saw that - but it adds an i2c binding which I don't yet have. I
> add i2c in the next series.
> 
> I will add that one i2c node here.

The clock doesn't /have/ to be represented by its full I2C source; you
could represent it as another global fixed-clock source until the I2C
node is available to act as a clock source.

Note that in order to actually use the tps6586x node to provide the
clock source, you'll need to write or modify the tps6586x's bindings to
document which clock sources it provides. I haven't actually looked at
the tps6586x's bindings at all; it's possible that part of the example
is entirely incorrect. In my original email I quoted above, the part
of the example I was caring about was that the CAR itself needs two
entries in its clocks property; I don't really care where they come from
at present.

-- 
nvpublic

Re: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Simon Glass]

Hi Stephen,

On Tue, Feb 28, 2012 at 9:32 AM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> Simon Glass wrote at Tuesday, February 28, 2012 10:21 AM:
>> On Mon, Feb 27, 2012 at 3:29 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> > On 02/27/2012 01:52 PM, Simon Glass wrote:
>> >> Add the definition of the oscillator clock frequency.
>> >
>> >> diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
>> >
>> >> +     clock@60006000 {
>> >> +             clocks = <&osc>;
>> >> +     };
>> >
>> > The CAR takes two clock inputs; one 32KHz clock (typically from the
>> > PMU/PMIC) and one from the oscillator. The 32KHz one is missing here. I
>> > guess this won't make any difference to U-Boot since it isn't using the
>> > clock inputs in the CAR driver, but it'd be best if the .dts file
>> > contained the correct content so it didn't act as an incorrect example.
>> > See the example in the binding documentation for what should be there.
>>
>> Yes I saw that - but it adds an i2c binding which I don't yet have. I
>> add i2c in the next series.
>>
>> I will add that one i2c node here.
>
> The clock doesn't /have/ to be represented by its full I2C source; you
> could represent it as another global fixed-clock source until the I2C
> node is available to act as a clock source.
>
> Note that in order to actually use the tps6586x node to provide the
> clock source, you'll need to write or modify the tps6586x's bindings to
> document which clock sources it provides. I haven't actually looked at
> the tps6586x's bindings at all; it's possible that part of the example
> is entirely incorrect. In my original email I quoted above, the part
> of the example I was caring about was that the CAR itself needs two
> entries in its clocks property; I don't really care where they come from
> at present.

I don't have tps6586x bindings and don't have support for them in
U-Boot at present. U-Boot also doesn't look at the clocks property so
I think your request is entirely about keeping things in sync with
what we expect will go into the kernel in the future.

I am going to add your binding, less the #clock-cells which U-Boot
currently can't support because it conflicts with the C preprocessor
(at some point I may look at a patch to use sed or some other means of
avoiding this).

Regards,
Simon

>
> --
> nvpublic
>

Re: [PATCH v6 15/20] tegra: fdt: Add function to return peripheral/clock ID

[Simon Glass]

Hi Stephen,

On Mon, Feb 27, 2012 at 3:41 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> On 02/27/2012 01:52 PM, Simon Glass wrote:
>> A common requirement is to find the clock ID for a peripheral. This is the
>> second cell of the 'clocks' property (the first being the phandle itself).
>
>> +int clock_decode_periph_id(const void *blob, int node)
>
>> +     valid = clock_periph_id_isvalid(id);
>
> clock_periph_id_isvalid() is not the correct function to use here; the
> code should be checking for invalid IDs in the CAR binding, not invalid
> IDs in the HW periph ID definition. They're different.
>
> Just to be explicit, the function you need here would be:
>
> int clkid_to_periphid(int clkid)
> {
>    if (clk_id > 95)
>        return -1;
>    switch (clk_id) {
>    case 1:
>    case 2:
>    case 7:
>    case 10:
>    case 20:
>    case 30:
>    case 35:
>    case 49:
>    case 56:
>    case 74:
>    case 77:
>    case 78:
>    case 79:
>    case 80:
>    case 81:
>    case 82:
>    case 83:
>    case 91:
>    case 95:
>        return -1;
>    default:
>        return clkid;
>    }
> }

Ick.

Why is 7 in there, and did you miss 76? Also U-Boot only goes up to 88
at present so should I change the first test to match?

Regards,
Simon

>
> --
> nvpublic
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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Re: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Stephen Warren]

Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
...
> I am going to add your binding, less the #clock-cells which U-Boot
> currently can't support because it conflicts with the C preprocessor
> (at some point I may look at a patch to use sed or some other means of
> avoiding this).

Out of curiosity, why does the C preprocessor come into it? Is U-Boot's
build process running cpp on the .dts files or something? That's non-
standard, although perhaps it could be a useful standard...

-- 
nvpublic

Re: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Simon Glass]

Hi Stephen,

On Tue, Feb 28, 2012 at 10:31 AM, Stephen Warren <swarren@nvidia.com> wrote:
> Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
> ...
>> I am going to add your binding, less the #clock-cells which U-Boot
>> currently can't support because it conflicts with the C preprocessor
>> (at some point I may look at a patch to use sed or some other means of
>> avoiding this).
>
> Out of curiosity, why does the C preprocessor come into it? Is U-Boot's
> build process running cpp on the .dts files or something? That's non-
> standard, although perhaps it could be a useful standard...

Yes, but at the moment we only use it for '/include/ ARCH_CPU_DTS'.

Still hoping your symbolic stuff will go in though.

Regards,
Simon

>
> --
> nvpublic
>

RE: [PATCH v6 15/20] tegra: fdt: Add function to return peripheral/clock ID

[Stephen Warren]

Simon Glass wrote at Tuesday, February 28, 2012 10:46 AM:
> On Mon, Feb 27, 2012 at 3:41 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> > On 02/27/2012 01:52 PM, Simon Glass wrote:
> >> A common requirement is to find the clock ID for a peripheral. This is the
> >> second cell of the 'clocks' property (the first being the phandle itself).
> >
> >> +int clock_decode_periph_id(const void *blob, int node)
> >
> >> +     valid = clock_periph_id_isvalid(id);
> >
> > clock_periph_id_isvalid() is not the correct function to use here; the
> > code should be checking for invalid IDs in the CAR binding, not invalid
> > IDs in the HW periph ID definition. They're different.
> >
> > Just to be explicit, the function you need here would be:
> >
> > int clkid_to_periphid(int clkid)
> > {
> >    if (clk_id > 95)
> >        return -1;
> >    switch (clk_id) {
> >    case 1:
> >    case 2:
> >    case 7:
> >    case 10:
> >    case 20:
> >    case 30:
> >    case 35:
> >    case 49:
> >    case 56:
> >    case 74:
> >    case 77:
> >    case 78:
> >    case 79:
> >    case 80:
> >    case 81:
> >    case 82:
> >    case 83:
> >    case 91:
> >    case 95:
> >        return -1;
> >    default:
> >        return clkid;
> >    }
> > }
> 
> Ick.
> 
> Why is 7 in there,

7 affects both the UART2 and VFIR clocks/blocks.

> and did you miss 76?

No, that's the undocumented "la" clock.

> Also U-Boot only goes up to 88
> at present so should I change the first test to match?

No, clocks 89, 90, 92, 93, and 94 are defined in the binding, which
matches the CLK_OUT_ENB registers in the Tegra CAR HW (albeit not the
CLK_RST registers, since there are some differences between the two).

-- 
nvpublic

Re: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Stephen Warren]

Simon Glass wrote at Tuesday, February 28, 2012 11:37 AM:
> On Tue, Feb 28, 2012 at 10:31 AM, Stephen Warren <swarren@nvidia.com> wrote:
> > Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
> > ...
> >> I am going to add your binding, less the #clock-cells which U-Boot
> >> currently can't support because it conflicts with the C preprocessor
> >> (at some point I may look at a patch to use sed or some other means of
> >> avoiding this).
> >
> > Out of curiosity, why does the C preprocessor come into it? Is U-Boot's
> > build process running cpp on the .dts files or something? That's non-
> > standard, although perhaps it could be a useful standard...
> 
> Yes, but at the moment we only use it for '/include/ ARCH_CPU_DTS'.

Uggh. That's going to make the device tree files look different between
the kernel and U-Boot:-( With # disallowed in particular, it's going to
prevent U-Boot from /ever/ using the correct protocols for parsing the
device tree. This seems like an extremely bad idea.

> Still hoping your symbolic stuff will go in though.

That looks extremely unlikely in its current form. Ideally, I will get
time to take Jon's or David's patches and push one of them forward to
provide a more complete solution, but it's a very long way out either way.

-- 
nvpublic

Re: [PATCH v6 15/20] tegra: fdt: Add function to return peripheral/clock ID

[Simon Glass]

Hi Stephen,

On Tue, Feb 28, 2012 at 10:37 AM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> Simon Glass wrote at Tuesday, February 28, 2012 10:46 AM:
>> On Mon, Feb 27, 2012 at 3:41 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> > On 02/27/2012 01:52 PM, Simon Glass wrote:
>> >> A common requirement is to find the clock ID for a peripheral. This is the
>> >> second cell of the 'clocks' property (the first being the phandle itself).
>> >
>> >> +int clock_decode_periph_id(const void *blob, int node)
>> >
>> >> +     valid = clock_periph_id_isvalid(id);
>> >
>> > clock_periph_id_isvalid() is not the correct function to use here; the
>> > code should be checking for invalid IDs in the CAR binding, not invalid
>> > IDs in the HW periph ID definition. They're different.
>> >
>> > Just to be explicit, the function you need here would be:
>> >
>> > int clkid_to_periphid(int clkid)
>> > {
>> >    if (clk_id > 95)
>> >        return -1;
>> >    switch (clk_id) {
>> >    case 1:
>> >    case 2:
>> >    case 7:
>> >    case 10:
>> >    case 20:
>> >    case 30:
>> >    case 35:
>> >    case 49:
>> >    case 56:
>> >    case 74:
>> >    case 77:
>> >    case 78:
>> >    case 79:
>> >    case 80:
>> >    case 81:
>> >    case 82:
>> >    case 83:
>> >    case 91:
>> >    case 95:
>> >        return -1;
>> >    default:
>> >        return clkid;
>> >    }
>> > }
>>
>> Ick.
>>
>> Why is 7 in there,
>
> 7 affects both the UART2 and VFIR clocks/blocks.
>
>> and did you miss 76?
>
> No, that's the undocumented "la" clock.
>
>> Also U-Boot only goes up to 88
>> at present so should I change the first test to match?
>
> No, clocks 89, 90, 92, 93, and 94 are defined in the binding, which
> matches the CLK_OUT_ENB registers in the Tegra CAR HW (albeit not the
> CLK_RST registers, since there are some differences between the two).

For both of your comments, since they aren't used in U-Boot, wouldn't
it be more correct to flag these as errors also? We would have to
update at least the clock.h header to support them.

Regards,
Simon

>
> --
> nvpublic
>

Re: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Simon Glass]

Hi Stephen,

On Tue, Feb 28, 2012 at 10:41 AM, Stephen Warren <swarren@nvidia.com> wrote:
> Simon Glass wrote at Tuesday, February 28, 2012 11:37 AM:
>> On Tue, Feb 28, 2012 at 10:31 AM, Stephen Warren <swarren@nvidia.com> wrote:
>> > Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
>> > ...
>> >> I am going to add your binding, less the #clock-cells which U-Boot
>> >> currently can't support because it conflicts with the C preprocessor
>> >> (at some point I may look at a patch to use sed or some other means of
>> >> avoiding this).
>> >
>> > Out of curiosity, why does the C preprocessor come into it? Is U-Boot's
>> > build process running cpp on the .dts files or something? That's non-
>> > standard, although perhaps it could be a useful standard...
>>
>> Yes, but at the moment we only use it for '/include/ ARCH_CPU_DTS'.
>
> Uggh. That's going to make the device tree files look different between
> the kernel and U-Boot:-( With # disallowed in particular, it's going to
> prevent U-Boot from /ever/ using the correct protocols for parsing the
> device tree. This seems like an extremely bad idea.

Until we change it in U-Boot, you mean. We could move to sed or pre-
and post-process the file to remove and re-insert the #.

>
>> Still hoping your symbolic stuff will go in though.
>
> That looks extremely unlikely in its current form. Ideally, I will get
> time to take Jon's or David's patches and push one of them forward to
> provide a more complete solution, but it's a very long way out either way.

That's a shame.

Regards,
Simon

>
> --
> nvpublic
>

Re: [PATCH v6 15/20] tegra: fdt: Add function to return peripheral/clock ID

[Stephen Warren]

Simon Glass wrote at Tuesday, February 28, 2012 11:44 AM:
> On Tue, Feb 28, 2012 at 10:37 AM, Stephen Warren <swarren@nvidia.com> wrote:
> > Simon Glass wrote at Tuesday, February 28, 2012 10:46 AM:
> >> On Mon, Feb 27, 2012 at 3:41 PM, Stephen Warren <swarren@nvidia.com> wrote:
> >> > On 02/27/2012 01:52 PM, Simon Glass wrote:
> >> >> A common requirement is to find the clock ID for a peripheral. This is the
> >> >> second cell of the 'clocks' property (the first being the phandle itself).
> >> >
> >> >> +int clock_decode_periph_id(const void *blob, int node)
> >> >
> >> >> +     valid = clock_periph_id_isvalid(id);
> >> >
> >> > clock_periph_id_isvalid() is not the correct function to use here; the
> >> > code should be checking for invalid IDs in the CAR binding, not invalid
> >> > IDs in the HW periph ID definition. They're different.
> >> >
> >> > Just to be explicit, the function you need here would be:
> >> >
> >> > int clkid_to_periphid(int clkid)
> >> > {
> >> >    if (clk_id > 95)
> >> >        return -1;
> >> >    switch (clk_id) {
> >> >    case 1:
> >> >    case 2:
> >> >    case 7:
> >> >    case 10:
> >> >    case 20:
> >> >    case 30:
> >> >    case 35:
> >> >    case 49:
> >> >    case 56:
> >> >    case 74:
> >> >    case 77:
> >> >    case 78:
> >> >    case 79:
> >> >    case 80:
> >> >    case 81:
> >> >    case 82:
> >> >    case 83:
> >> >    case 91:
> >> >    case 95:
> >> >        return -1;
> >> >    default:
> >> >        return clkid;
> >> >    }
> >> > }
> >>
> >> Ick.
> >>
> >> Why is 7 in there,
> >
> > 7 affects both the UART2 and VFIR clocks/blocks.
> >
> >> and did you miss 76?
> >
> > No, that's the undocumented "la" clock.
> >
> >> Also U-Boot only goes up to 88
> >> at present so should I change the first test to match?
> >
> > No, clocks 89, 90, 92, 93, and 94 are defined in the binding, which
> > matches the CLK_OUT_ENB registers in the Tegra CAR HW (albeit not the
> > CLK_RST registers, since there are some differences between the two).
> 
> For both of your comments, since they aren't used in U-Boot, wouldn't
> it be more correct to flag these as errors also? We would have to
> update at least the clock.h header to support them.

It's probably more correct to update the periph_id enum to define all
the valid values, but either way is fine.

-- 
nvpublic

Re: [U-Boot] [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Albert ARIBAUD]

Le 28/02/2012 19:46, Simon Glass a écrit :
> Hi Stephen,
>
> On Tue, Feb 28, 2012 at 10:41 AM, Stephen Warren<swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>  wrote:
>> Simon Glass wrote at Tuesday, February 28, 2012 11:37 AM:
>>> On Tue, Feb 28, 2012 at 10:31 AM, Stephen Warren<swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>  wrote:
>>>> Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
>>>> ...
>>>>> I am going to add your binding, less the #clock-cells which U-Boot
>>>>> currently can't support because it conflicts with the C preprocessor
>>>>> (at some point I may look at a patch to use sed or some other means of
>>>>> avoiding this).
>>>>
>>>> Out of curiosity, why does the C preprocessor come into it? Is U-Boot's
>>>> build process running cpp on the .dts files or something? That's non-
>>>> standard, although perhaps it could be a useful standard...
>>>
>>> Yes, but at the moment we only use it for '/include/ ARCH_CPU_DTS'.
>>
>> Uggh. That's going to make the device tree files look different between
>> the kernel and U-Boot:-( With # disallowed in particular, it's going to
>> prevent U-Boot from /ever/ using the correct protocols for parsing the
>> device tree. This seems like an extremely bad idea.
>
> Until we change it in U-Boot, you mean. We could move to sed or pre-
> and post-process the file to remove and re-insert the #.

Rather, to convert # signs into something that the DTS cannot contain 
and the compiler can withstand (and it should be printable ASCII, too). 
is '##' a good candidate?

If so, a forward conversion would e.g. map '/include/' to '#include' and 
any '#' to '##', and the reverse conversion would turn all '##' to '#'.

But something that simple is bound to be wrong in some way...

Amicalement,
-- 
Albert.

Re: [PATCH v6 15/20] tegra: fdt: Add function to return peripheral/clock ID

[Simon Glass]

Hi Stephen,

On Tue, Feb 28, 2012 at 10:51 AM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> Simon Glass wrote at Tuesday, February 28, 2012 11:44 AM:
>> On Tue, Feb 28, 2012 at 10:37 AM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> > Simon Glass wrote at Tuesday, February 28, 2012 10:46 AM:
>> >> On Mon, Feb 27, 2012 at 3:41 PM, Stephen Warren <swarren@nvidia.com> wrote:
>> >> > On 02/27/2012 01:52 PM, Simon Glass wrote:
>> >> >> A common requirement is to find the clock ID for a peripheral. This is the
>> >> >> second cell of the 'clocks' property (the first being the phandle itself).
>> >> >
>> >> >> +int clock_decode_periph_id(const void *blob, int node)
>> >> >
>> >> >> +     valid = clock_periph_id_isvalid(id);
>> >> >
>> >> > clock_periph_id_isvalid() is not the correct function to use here; the
>> >> > code should be checking for invalid IDs in the CAR binding, not invalid
>> >> > IDs in the HW periph ID definition. They're different.
>> >> >
>> >> > Just to be explicit, the function you need here would be:
>> >> >
>> >> > int clkid_to_periphid(int clkid)
>> >> > {
>> >> >    if (clk_id > 95)
>> >> >        return -1;
>> >> >    switch (clk_id) {
>> >> >    case 1:
>> >> >    case 2:
>> >> >    case 7:
>> >> >    case 10:
>> >> >    case 20:
>> >> >    case 30:
>> >> >    case 35:
>> >> >    case 49:
>> >> >    case 56:
>> >> >    case 74:
>> >> >    case 77:
>> >> >    case 78:
>> >> >    case 79:
>> >> >    case 80:
>> >> >    case 81:
>> >> >    case 82:
>> >> >    case 83:
>> >> >    case 91:
>> >> >    case 95:
>> >> >        return -1;
>> >> >    default:
>> >> >        return clkid;
>> >> >    }
>> >> > }
>> >>
>> >> Ick.
>> >>
>> >> Why is 7 in there,
>> >
>> > 7 affects both the UART2 and VFIR clocks/blocks.
>> >
>> >> and did you miss 76?
>> >
>> > No, that's the undocumented "la" clock.
>> >
>> >> Also U-Boot only goes up to 88
>> >> at present so should I change the first test to match?
>> >
>> > No, clocks 89, 90, 92, 93, and 94 are defined in the binding, which
>> > matches the CLK_OUT_ENB registers in the Tegra CAR HW (albeit not the
>> > CLK_RST registers, since there are some differences between the two).
>>
>> For both of your comments, since they aren't used in U-Boot, wouldn't
>> it be more correct to flag these as errors also? We would have to
>> update at least the clock.h header to support them.
>
> It's probably more correct to update the periph_id enum to define all
> the valid values, but either way is fine.

OK - BTW what does 'LA' stand for?

Regards,
Simon

>
> --
> nvpublic
>

RE: [PATCH v6 15/20] tegra: fdt: Add function to return peripheral/clock ID

[Stephen Warren]

Simon Glass wrote at Tuesday, February 28, 2012 4:50 PM:
> On Tue, Feb 28, 2012 at 10:51 AM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> > Simon Glass wrote at Tuesday, February 28, 2012 11:44 AM:
> >> On Tue, Feb 28, 2012 at 10:37 AM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
...
> >> >> and did you miss 76?
> >> >
> >> > No, that's the undocumented "la" clock.
....
> OK - BTW what does 'LA' stand for?

Sorry, I don't know; it's not documented. I just confirmed it exists.

-- 
nvpublic

Re: [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Simon Glass]

Hi Albert,

On Tue, Feb 28, 2012 at 2:16 PM, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Le 28/02/2012 19:46, Simon Glass a écrit :
>
>> Hi Stephen,
>>
>> On Tue, Feb 28, 2012 at 10:41 AM, Stephen Warren<swarren@nvidia.com>
>>  wrote:
>>>
>>> Simon Glass wrote at Tuesday, February 28, 2012 11:37 AM:
>>>>
>>>> On Tue, Feb 28, 2012 at 10:31 AM, Stephen Warren<swarren@nvidia.com>
>>>>  wrote:
>>>>>
>>>>> Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
>>>>> ...
>>>>>>
>>>>>> I am going to add your binding, less the #clock-cells which U-Boot
>>>>>> currently can't support because it conflicts with the C preprocessor
>>>>>> (at some point I may look at a patch to use sed or some other means of
>>>>>> avoiding this).
>>>>>
>>>>>
>>>>> Out of curiosity, why does the C preprocessor come into it? Is U-Boot's
>>>>> build process running cpp on the .dts files or something? That's non-
>>>>> standard, although perhaps it could be a useful standard...
>>>>
>>>>
>>>> Yes, but at the moment we only use it for '/include/ ARCH_CPU_DTS'.
>>>
>>>
>>> Uggh. That's going to make the device tree files look different between
>>> the kernel and U-Boot:-( With # disallowed in particular, it's going to
>>> prevent U-Boot from /ever/ using the correct protocols for parsing the
>>> device tree. This seems like an extremely bad idea.
>>
>>
>> Until we change it in U-Boot, you mean. We could move to sed or pre-
>> and post-process the file to remove and re-insert the #.
>
>
> Rather, to convert # signs into something that the DTS cannot contain and
> the compiler can withstand (and it should be printable ASCII, too). is '##'
> a good candidate?
>
> If so, a forward conversion would e.g. map '/include/' to '#include' and any
> '#' to '##', and the reverse conversion would turn all '##' to '#'.
>
> But something that simple is bound to be wrong in some way...

It seems reasonable, although the /include/ is handled by the dtc
itself. If we bypath that then line number reporting won't work.
However I do have problems getting dtc to find its include files - I
wish it had a -I option.

I will take a look at this in a few weeks once this series in is and I
have looked at the include file problem in more detail.

Regards,
Simon

>
> Amicalement,
> --
> Albert.

Re: [U-Boot] [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Tom Rini]

On Tue, Feb 28, 2012 at 10:41:15AM -0800, Stephen Warren wrote:
> Simon Glass wrote at Tuesday, February 28, 2012 11:37 AM:
> > On Tue, Feb 28, 2012 at 10:31 AM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> > > Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
> > > ...
> > >> I am going to add your binding, less the #clock-cells which U-Boot
> > >> currently can't support because it conflicts with the C preprocessor
> > >> (at some point I may look at a patch to use sed or some other means of
> > >> avoiding this).
> > >
> > > Out of curiosity, why does the C preprocessor come into it? Is U-Boot's
> > > build process running cpp on the .dts files or something? That's non-
> > > standard, although perhaps it could be a useful standard...
> > 
> > Yes, but at the moment we only use it for '/include/ ARCH_CPU_DTS'.
> 
> Uggh. That's going to make the device tree files look different between
> the kernel and U-Boot:-( With # disallowed in particular, it's going to
> prevent U-Boot from /ever/ using the correct protocols for parsing the
> device tree. This seems like an extremely bad idea.

Keeping my TI hat on, I think it'd be a bad idea to have dts stuff
divergent from the kernel.  Have you raised the problem you're trying to
solve to the general DT gurus?  My very high level hope is that someday
we can have them shared between kernel and u-boot (either directly or
something silly like a .dtss that spits out a kernel dts and a u-boot
dts).  Going with a manual sync from kernel form to u-boot form seems
like adding a burden on ourselves we might not have to.

-- 
Tom

Re: [U-Boot] [PATCH v6 11/20] tegra: fdt: Add clock bindings for Tegra2 Seaboard

[Simon Glass]

Hi Tom,

On Mon, Mar 5, 2012 at 12:46 PM, Tom Rini <trini-l0cyMroinI0@public.gmane.org> wrote:
> On Tue, Feb 28, 2012 at 10:41:15AM -0800, Stephen Warren wrote:
>> Simon Glass wrote at Tuesday, February 28, 2012 11:37 AM:
>> > On Tue, Feb 28, 2012 at 10:31 AM, Stephen Warren <swarren@nvidia.com> wrote:
>> > > Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
>> > > ...
>> > >> I am going to add your binding, less the #clock-cells which U-Boot
>> > >> currently can't support because it conflicts with the C preprocessor
>> > >> (at some point I may look at a patch to use sed or some other means of
>> > >> avoiding this).
>> > >
>> > > Out of curiosity, why does the C preprocessor come into it? Is U-Boot's
>> > > build process running cpp on the .dts files or something? That's non-
>> > > standard, although perhaps it could be a useful standard...
>> >
>> > Yes, but at the moment we only use it for '/include/ ARCH_CPU_DTS'.
>>
>> Uggh. That's going to make the device tree files look different between
>> the kernel and U-Boot:-( With # disallowed in particular, it's going to
>> prevent U-Boot from /ever/ using the correct protocols for parsing the
>> device tree. This seems like an extremely bad idea.
>
> Keeping my TI hat on, I think it'd be a bad idea to have dts stuff
> divergent from the kernel.  Have you raised the problem you're trying to
> solve to the general DT gurus?  My very high level hope is that someday
> we can have them shared between kernel and u-boot (either directly or
> something silly like a .dtss that spits out a kernel dts and a u-boot
> dts).  Going with a manual sync from kernel form to u-boot form seems
> like adding a burden on ourselves we might not have to.

I agree, of course. I think the best solution may be to implement
search paths in dtc. I sent a patch today so let's see what people
think.

It is even worse when we copy the .dts and .dtsi files somewhere else
(e.g. losing the original directory tree relationship by copying all
into one directory).

Regards,
Simon

>
> --
> Tom