From: Jon Hunter <jonathanh@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Kartik Rajput <kkartik@nvidia.com>
Cc: jassisinghbrar@gmail.com, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] mailbox: tegra-hsp: Define dimensioning masks in soc data
Date: Thu, 27 Feb 2025 18:13:36 +0000 [thread overview]
Message-ID: <4bfb33c7-5d12-4862-bad3-495ce5fd70ed@nvidia.com> (raw)
In-Reply-To: <hgvxugls732nt5yfoqygvxn52x73ioh4qpbbmu6swwmafsrmm7@w2gcbjinmujj>
On 27/02/2025 10:35, Thierry Reding wrote:
> On Thu, Jan 23, 2025 at 06:16:32PM +0530, Kartik Rajput wrote:
>> Tegra264 has updated HSP_INT_DIMENSIONING register as follows:
>> * nSI is now BIT17:BIT21.
>> * nDB is now BIT12:BIT16.
>>
>> Currently, we are using a static macro HSP_nINT_MASK to get the values
>> from HSP_INT_DIMENSIONING register. This results in wrong values for nSI
>> for HSP instances that supports 16 shared interrupts.
>>
>> Define dimensioning masks in soc data and use them to parse nSI, nDB,
>> nAS, nSS & nSM values.
>>
>> Fixes: 602dbbacc3ef ("mailbox: tegra: add support for Tegra264")
>> Cc: stable@vger.kernel.org
>>
>> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
>
> Maybe remove the blank line between the Cc: and S-o-b: tags. Also, "soc"
> -> "SoC" in the subject and commit message. With that:
>
> Acked-by: Thierry Reding <treding@nvidia.com>
FWIW ...
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Thanks!
Jon
--
nvpublic
next prev parent reply other threads:[~2025-02-27 18:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-23 12:46 [PATCH] mailbox: tegra-hsp: Define dimensioning masks in soc data Kartik Rajput
2025-02-27 10:35 ` Thierry Reding
2025-02-27 18:13 ` Jon Hunter [this message]
2025-03-01 16:42 ` Jassi Brar
2025-03-03 15:52 ` Thierry Reding
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