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Mon, 8 Mar 2021 18:32:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT030.mail.protection.outlook.com (10.13.172.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.3912.17 via Frontend Transport; Mon, 8 Mar 2021 18:32:18 +0000 Received: from [10.2.163.31] (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 8 Mar 2021 18:32:17 +0000 Subject: Re: [PATCH v1 3/5] dt-bindings: arm: Add cpu-idle-states to Tegra194 CPU nodes To: Sudeep Holla CC: , , , , , , , , , References: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> <1614838092-30398-4-git-send-email-skomatineni@nvidia.com> <20210308043755.llvdsuz2jwvweovb@bogus> From: Sowjanya Komatineni Message-ID: <4cebf482-a2f8-5a79-a2f6-4ccd7d31c6ad@nvidia.com> Date: Mon, 8 Mar 2021 10:32:17 -0800 User-Agent: Mozilla/5.0 (X11; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2021 18:32:18.9403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f0cf7d4-9397-4f87-99bb-08d8e2608182 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3435 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On 3/7/21 8:37 PM, Sudeep Holla wrote: > On Wed, Mar 03, 2021 at 10:08:10PM -0800, Sowjanya Komatineni wrote: >> This patch adds cpu-idle-states and corresponding state nodes to >> Tegra194 CPU in dt-binding document >> > I see that this platform has PSCI support. Can you care to explain why > you need additional DT bindings and driver for PSCI based CPU suspend. > Until the reasons are convincing, consider NACK from my side for this > driver and DT bindings. You should be really using those bindings and > the driver may be with minor changes there. > MCE firmware is in charge of state transition for Tegra194 carmel CPUs. For run-time state transitions, need to provide state request along with its residency time to MCE firmware which is running in the background. State min residency is updated into power_state value along with state id that is passed to psci_cpu_suspend_enter Also states cross-over idle times need to be provided to MCE firmware. MCE firmware decides on state transition based on these inputs along with its background work load. So, Tegra specific CPU idle driver is required mainly to provide cross-over thresholds from DT and run time idle state information to MCE firmware through Tegra MCE communication APIs. Allowing cross-over threshold through DT allows users to vary idle time thresholds for state transitions based on different use-cases.