Re: [PATCH v7 06/13] PCI: tegra194: Disable direct speed change for EP

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

On 05/03/26 3:13 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:24:41PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> Disable direct speed change for the Endpoint to prevent it from initiating
>> the speed change post physical layer link up at gen1. This leaves the speed
>> change ownership with the host.
>>
> 
> Why?
> 
> - Mani
In pre silicon sim tests our HW team identified that Endpoint is trying 
to initiate speed change after secondary bus reset. So, our HW team 
recommended to disable direct speed change feature in Endpoint to keep 
the speed change control with host.

- Manikanta

> 
>> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V1 -> V7: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 7dcf3e3596dd..2da3478f0b5f 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1805,6 +1805,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>>   
>>   	reset_control_deassert(pcie->core_rst);
>>   
>> +	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
>> +	val &= ~PORT_LOGIC_SPEED_CHANGE;
>> +	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
>> +
>>   	if (pcie->update_fc_fixup) {
>>   		val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
>>   		val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic