[PATCH v4 1/5] ARM: tegra: dts: Add pwm label

[PATCH v4 1/5] ARM: tegra: dts: Add pwm label

[Thierry Reding]

PWM devices can be referenced in the DT by phandle and per-chip index.
In order for this to work properly, the PWM controller needs to have a
label attached to it.

Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
---
 arch/arm/boot/dts/tegra20.dtsi | 2 +-
 arch/arm/boot/dts/tegra30.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 405d167..67a6cd9 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -123,7 +123,7 @@
 		status = "disabled";
 	};
 
-	pwm {
+	pwm: pwm {
 		compatible = "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3e4334d..b1497c7 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -117,7 +117,7 @@
 		status = "disabled";
 	};
 
-	pwm {
+	pwm: pwm {
 		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
-- 
1.7.12

[PATCH v4 2/5] ARM: tegra: Add Avionic Design Tamonten support

[Thierry Reding]

The Tamonten is an NVIDIA Tegra2 based system-on-module (SOM) that is
designed to cover a broad range of applications.

Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
---
Changes in v4:
- synchronize regulators with Harmony for consistency
- set bus width of MMC to 4

 arch/arm/boot/dts/tegra20-tamonten.dtsi | 438 ++++++++++++++++++++++++++++++++
 1 file changed, 438 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsi

diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
new file mode 100644
index 0000000..4bdcf1b
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,438 @@
+/include/ "tegra20.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten SOM";
+	compatible = "ad,tamonten", "nvidia,tegra20";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	pinmux {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+					"spia", "spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			dta {
+				nvidia,pins = "dta", "dtd";
+				nvidia,function = "sdio2";
+			};
+			dtb {
+				nvidia,pins = "dtb", "dtc", "dte";
+				nvidia,function = "rsvd1";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint", "pta";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uarta";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
+					"lhs", "lm0", "lm1", "lpp", "lpw0",
+					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
+					"lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+					"cdev1", "cdev2", "dap1", "dtb", "gma",
+					"gmb", "gmc", "gmd", "gme", "gpu7",
+					"gpv", "i2cp", "pta", "rm", "slxa",
+					"slxk", "spia", "spib", "uac";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <0>;
+			};
+			conf_csus {
+				nvidia,pins = "csus", "spid", "spif";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+					"dtc", "dte", "dtf", "gpu", "sdio1",
+					"slxc", "slxd", "spdi", "spdo", "spig",
+					"uda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			conf_ddc {
+				nvidia,pins = "ddc", "dta", "dtd", "kbca",
+					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+					"sdc";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0", "owc", "sdb";
+				nvidia,tristate = <1>;
+			};
+			conf_irrx {
+				nvidia,pins = "irrx", "irtx", "sdd", "spic",
+					"spie", "spih", "uaa", "uab", "uad",
+					"uca", "ucb";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <2>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "pmc";
+				nvidia,tristate = <0>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <1>;
+			};
+		};
+	};
+
+	i2s@70002800 {
+		status = "okay";
+	};
+
+	serial@70006300 {
+		clock-frequency = <216000000>;
+		status = "okay";
+	};
+
+	i2c@7000c000 {
+		clock-frequency = <400000>;
+		status = "okay";
+	};
+
+	i2c@7000d000 {
+		clock-frequency = <400000>;
+		status = "okay";
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator@0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator@1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				regulator@2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator@3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				regulator@4 {
+					reg = <4>;
+					regulator-compatible = "ldo0";
+					regulator-name = "vdd_ldo0,vddio_pex_clk";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				regulator@5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator@6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				regulator@7 {
+					reg = <7>;
+					regulator-compatible = "ldo3";
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator@8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				regulator@9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator@10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+				};
+
+				regulator@11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				regulator@12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator@13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator@14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
+	};
+
+	usb@c5008000 {
+		status = "okay";
+	};
+
+	sdhci@c8000600 {
+		cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+		bus-width = <4>;
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+	};
+};
-- 
1.7.12

[PATCH v4 3/5] ARM: tegra: Add Avionic Design Plutux support

[Thierry Reding]

The Plutux is a set-top box device based on the Tamonten SOM and can be
connected to a display via HDMI.

Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
---
Changes in v4:
- based on tegra20-tamonten.dtsi
- rename compatible of sound property to match device name

 arch/arm/boot/dts/tegra20-plutux.dts | 52 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/Makefile.boot    |  1 +
 2 files changed, 53 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-plutux.dts

diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
new file mode 100644
index 0000000..cdcdb45
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -0,0 +1,52 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Plutux board";
+	compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
+
+	i2c@7000c000 {
+		wm8903: wm8903@1a {
+			compatible = "wlf,wm8903";
+			reg = <0x1a>;
+			interrupt-parent = <&gpio>;
+			interrupts = <187 0x04>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			micdet-cfg = <0>;
+			micdet-delay = <100>;
+			gpio-cfg = <0xffffffff
+				    0xffffffff
+				    0
+				    0xffffffff
+				    0xffffffff>;
+		};
+	};
+
+	sound {
+		compatible = "ad,tegra-audio-plutux",
+			     "nvidia,tegra-audio-wm8903";
+		nvidia,model = "Avionic Design Plutux";
+
+		nvidia,audio-routing =
+			"Headphone Jack", "HPOUTR",
+			"Headphone Jack", "HPOUTL",
+			"Int Spk", "ROP",
+			"Int Spk", "RON",
+			"Int Spk", "LOP",
+			"Int Spk", "LON",
+			"Mic Jack", "MICBIAS",
+			"IN1L", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8903>;
+
+		nvidia,spkr-en-gpios = <&wm8903 2 0>;
+		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+	};
+};
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 6e35207..63f1d61 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -4,6 +4,7 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00800000
 
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-plutux.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb
-- 
1.7.12

[PATCH v4 4/5] ARM: tegra: Add Avionic Design Medcom-Wide support

[Thierry Reding]

The Medcom is a 16:9 15" terminal that is used for patient infotainment
in hospitals.

Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
---
Changes in v4:
- based on tegra20-tamonten.dtsi
- rename compatible of sound property to match device
- rename DTS file to match device name

 arch/arm/boot/dts/tegra20-medcom-wide.dts | 60 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/Makefile.boot         |  1 +
 2 files changed, 61 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dts

diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
new file mode 100644
index 0000000..d2ff5ab
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -0,0 +1,60 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Medcom-Wide board";
+	compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
+
+	i2c@7000c000 {
+		wm8903: wm8903@1a {
+			compatible = "wlf,wm8903";
+			reg = <0x1a>;
+			interrupt-parent = <&gpio>;
+			interrupts = <187 0x04>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			micdet-cfg = <0>;
+			micdet-delay = <100>;
+			gpio-cfg = <0xffffffff
+				    0xffffffff
+				    0
+				    0xffffffff
+				    0xffffffff>;
+		};
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 5000000>;
+
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+	};
+
+	sound {
+		compatible = "ad,tegra-audio-wm8903-medcom-wide",
+			     "nvidia,tegra-audio-wm8903";
+		nvidia,model = "Avionic Design Medcom-Wide";
+
+		nvidia,audio-routing =
+			"Headphone Jack", "HPOUTR",
+			"Headphone Jack", "HPOUTL",
+			"Int Spk", "ROP",
+			"Int Spk", "RON",
+			"Int Spk", "LOP",
+			"Int Spk", "LON",
+			"Mic Jack", "MICBIAS",
+			"IN1L", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8903>;
+
+		nvidia,spkr-en-gpios = <&wm8903 2 0>;
+		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+	};
+};
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 63f1d61..020548a 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -3,6 +3,7 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00800000
 
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-medcom-wide.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-plutux.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
-- 
1.7.12

[PATCH v4 5/5] ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support

[Thierry Reding]

The Tamonten Evaluation Carrier is an evaluation board for the Tamonten
SOM. More information is available here:

	http://www.avionic-design.de/en/products/nvidia-tegra-tamonten-system-en/nvidia-tegra-tamonten-evboard-en.html

Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
---
Changes in v4:
- based on tegra20-tamonten.dtsi
- rename compatible of sound property to match device

 arch/arm/boot/dts/tegra20-tec.dts | 55 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/Makefile.boot |  1 +
 2 files changed, 56 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-tec.dts

diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
new file mode 100644
index 0000000..49c7e36
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -0,0 +1,55 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten Evaluation Carrier";
+	compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
+
+	i2c@7000c000 {
+		clock-frequency = <400000>;
+		status = "okay";
+
+		wm8903: wm8903@1a {
+			compatible = "wlf,wm8903";
+			reg = <0x1a>;
+			interrupt-parent = <&gpio>;
+			interrupts = <187 0x04>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			micdet-cfg = <0>;
+			micdet-delay = <100>;
+			gpio-cfg = <0xffffffff
+				    0xffffffff
+				    0
+				    0xffffffff
+				    0xffffffff>;
+		};
+	};
+
+	sound {
+		compatible = "ad,tegra-audio-wm8903-tec",
+			     "nvidia,tegra-audio-wm8903";
+		nvidia,model = "Avionic Design TEC";
+
+		nvidia,audio-routing =
+			"Headphone Jack", "HPOUTR",
+			"Headphone Jack", "HPOUTL",
+			"Int Spk", "ROP",
+			"Int Spk", "RON",
+			"Int Spk", "LOP",
+			"Int Spk", "LON",
+			"Mic Jack", "MICBIAS",
+			"IN1L", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8903>;
+
+		nvidia,spkr-en-gpios = <&wm8903 2 0>;
+		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+	};
+};
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 020548a..54c16aa 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-medcom-wide.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-plutux.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-tec.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
-- 
1.7.12

Re: [PATCH v4 2/5] ARM: tegra: Add Avionic Design Tamonten support

[Stephen Warren]

On 09/18/2012 08:39 AM, Thierry Reding wrote:
> The Tamonten is an NVIDIA Tegra2 based system-on-module (SOM) that is
> designed to cover a broad range of applications.

> diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
...
> +		pmic: tps6586x@34 {
...
> +			regulators {
...
> +					regulator-name = "vdd_sys";
...
> +					regulator-name = "vdd_sm0,vdd_core";
...
> +					regulator-name = "vdd_sm1,vdd_cpu";
...
> +					regulator-name = "vdd_sm2,vin_ldo*";
...
> +					regulator-name = "vdd_ldo0,vddio_pex_clk";

etc.

I just wanted to confirm that those regulator-name values truly are the
signal names in the schematic and not something copied blindly from the
Harmony .dts file without any updates. Same for the voltages.

Re: [PATCH v4 3/5] ARM: tegra: Add Avionic Design Plutux support

[Stephen Warren]

On 09/18/2012 08:39 AM, Thierry Reding wrote:
> The Plutux is a set-top box device based on the Tamonten SOM and can be
> connected to a display via HDMI.

> diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts

> +	sound {
> +		compatible = "ad,tegra-audio-plutux",
> +			     "nvidia,tegra-audio-wm8903";
> +		nvidia,model = "Avionic Design Plutux";
> +
> +		nvidia,audio-routing =
> +			"Headphone Jack", "HPOUTR",
> +			"Headphone Jack", "HPOUTL",
> +			"Int Spk", "ROP",
> +			"Int Spk", "RON",
> +			"Int Spk", "LOP",
> +			"Int Spk", "LON",
> +			"Mic Jack", "MICBIAS",
> +			"IN1L", "Mic Jack";
> +
> +		nvidia,i2s-controller = <&tegra_i2s1>;
> +		nvidia,audio-codec = <&wm8903>;
> +
> +		nvidia,spkr-en-gpios = <&wm8903 2 0>;
> +		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> +		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
> +		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */

Does your board really have all of those GPIOs? Having both
int-mic-en-gpios and ext-mic-en-gpios is something pretty unique to
Harmony so far, and also a pretty broken HW design, so I'd hope people
haven't copied it.

Re: [PATCH v4 2/5] ARM: tegra: Add Avionic Design Tamonten support

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1034 bytes --]

On Wed, Sep 19, 2012 at 09:55:30AM -0600, Stephen Warren wrote:
> On 09/18/2012 08:39 AM, Thierry Reding wrote:
> > The Tamonten is an NVIDIA Tegra2 based system-on-module (SOM) that is
> > designed to cover a broad range of applications.
> 
> > diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
> ...
> > +		pmic: tps6586x@34 {
> ...
> > +			regulators {
> ...
> > +					regulator-name = "vdd_sys";
> ...
> > +					regulator-name = "vdd_sm0,vdd_core";
> ...
> > +					regulator-name = "vdd_sm1,vdd_cpu";
> ...
> > +					regulator-name = "vdd_sm2,vin_ldo*";
> ...
> > +					regulator-name = "vdd_ldo0,vddio_pex_clk";
> 
> etc.
> 
> I just wanted to confirm that those regulator-name values truly are the
> signal names in the schematic and not something copied blindly from the
> Harmony .dts file without any updates. Same for the voltages.

I believe the schematics were blindly copied from the Harmony reference
design. =) But I'll double check.

Thierry

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Re: [PATCH v4 3/5] ARM: tegra: Add Avionic Design Plutux support

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1861 bytes --]

On Wed, Sep 19, 2012 at 09:56:55AM -0600, Stephen Warren wrote:
> On 09/18/2012 08:39 AM, Thierry Reding wrote:
> > The Plutux is a set-top box device based on the Tamonten SOM and can be
> > connected to a display via HDMI.
> 
> > diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
> 
> > +	sound {
> > +		compatible = "ad,tegra-audio-plutux",
> > +			     "nvidia,tegra-audio-wm8903";
> > +		nvidia,model = "Avionic Design Plutux";
> > +
> > +		nvidia,audio-routing =
> > +			"Headphone Jack", "HPOUTR",
> > +			"Headphone Jack", "HPOUTL",
> > +			"Int Spk", "ROP",
> > +			"Int Spk", "RON",
> > +			"Int Spk", "LOP",
> > +			"Int Spk", "LON",
> > +			"Mic Jack", "MICBIAS",
> > +			"IN1L", "Mic Jack";
> > +
> > +		nvidia,i2s-controller = <&tegra_i2s1>;
> > +		nvidia,audio-codec = <&wm8903>;
> > +
> > +		nvidia,spkr-en-gpios = <&wm8903 2 0>;
> > +		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
> > +		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
> > +		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
> 
> Does your board really have all of those GPIOs? Having both
> int-mic-en-gpios and ext-mic-en-gpios is something pretty unique to
> Harmony so far,

The hardware was kept as close to Harmony as possible on purpose in
order to reduce the time needed for customization. This is obviously no
longer true now because the hardware is already about 18 months old but
you can't change hardware retroactively...

Again I'll make sure to double check this against the schematics but I'm
pretty sure these are the connections.

> and also a pretty broken HW design, so I'd hope people
> haven't copied it.

Would you mind explaining why it is broken? I haven't really been
involved with the codec parts so I don't have very deep insights.

Thierry

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Re: [PATCH v4 3/5] ARM: tegra: Add Avionic Design Plutux support

[Stephen Warren]

On 09/19/2012 10:42 AM, Thierry Reding wrote:
> On Wed, Sep 19, 2012 at 09:56:55AM -0600, Stephen Warren wrote:
>> On 09/18/2012 08:39 AM, Thierry Reding wrote:
>>> The Plutux is a set-top box device based on the Tamonten SOM
>>> and can be connected to a display via HDMI.
>> 
>>> diff --git a/arch/arm/boot/dts/tegra20-plutux.dts
>>> b/arch/arm/boot/dts/tegra20-plutux.dts
>> 
>>> +	sound { +		compatible = "ad,tegra-audio-plutux", +
>>> "nvidia,tegra-audio-wm8903"; +		nvidia,model = "Avionic Design
>>> Plutux"; + +		nvidia,audio-routing = +			"Headphone Jack",
>>> "HPOUTR", +			"Headphone Jack", "HPOUTL", +			"Int Spk",
>>> "ROP", +			"Int Spk", "RON", +			"Int Spk", "LOP", +			"Int
>>> Spk", "LON", +			"Mic Jack", "MICBIAS", +			"IN1L", "Mic
>>> Jack"; + +		nvidia,i2s-controller = <&tegra_i2s1>; +
>>> nvidia,audio-codec = <&wm8903>; + +		nvidia,spkr-en-gpios =
>>> <&wm8903 2 0>; +		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio
>>> PW2 */ +		nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0
>>> */ +		nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
>> 
>> Does your board really have all of those GPIOs? Having both 
>> int-mic-en-gpios and ext-mic-en-gpios is something pretty unique
>> to Harmony so far,
> 
> The hardware was kept as close to Harmony as possible on purpose
> in order to reduce the time needed for customization. This is
> obviously no longer true now because the hardware is already about
> 18 months old but you can't change hardware retroactively...
> 
> Again I'll make sure to double check this against the schematics
> but I'm pretty sure these are the connections.
> 
>> and also a pretty broken HW design, so I'd hope people haven't
>> copied it.
> 
> Would you mind explaining why it is broken? I haven't really been 
> involved with the codec parts so I don't have very deep insights.

The issue is roughly that there's only 1 micbias signal, yet two
microphones, so if micbias current indicates that a mic is attached,
there's no way to know which mic is attached.

The driver currently hard-codes the int mic GPIO to disabled and the
ext mic GPIO to enabled, essentially completely ignoring the internal
mic completely and pretending there's just one. On Harmony, the int
mic is actually a header that you can optionally connect a mic to, and
hence I'd assume most people don't, and hence just use the ext mic
anyway. hence the driver's behaviour is pretty reasonable. Hopefully
that behaviour will work fine for your board too? If not, the driver
would probably need to grow a control to select between the two mics,
but I suppose that wouldn't affect the DT.