[PATCH] ARM: tegra30: clk: Fix output_rate overflow

[PATCH] ARM: tegra30: clk: Fix output_rate overflow

[Mark Zhang]

Change the type of variable from "unsigned long" to "u64".
This avoids the overflow while clock rate calculating.

Signed-off-by: Mark Zhang <markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/tegra30_clocks.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 5cd502c..e9de5df 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1199,7 +1199,7 @@ static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 {
 	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long input_rate = *prate;
-	unsigned long output_rate = *prate;
+	u64 output_rate = *prate;
 	const struct clk_pll_freq_table *sel;
 	struct clk_pll_freq_table cfg;
 	int mul;
-- 
1.7.9.5

Re: [PATCH] ARM: tegra30: clk: Fix output_rate overflow

[Stephen Warren]

On 10/16/2012 02:31 AM, Mark Zhang wrote:
> Change the type of variable from "unsigned long" to "u64".
> This avoids the overflow while clock rate calculating.

Thanks, applied to Tegra's for-3.7/fixes-for-rc2 branch.

Prashant, this same bug was found before in another round_rate() or
similar function, and I'd asked you to audit the entire Tegra clock
driver for any similar issues. Could you (and/or Mark) please take
another look at the entire driver to make sure we don't keep finding
this issue clock-by-clock. Thanks.