* [PATCH V2 1/2] ARM: tegra: dt: add L2 cache controller
@ 2012-10-29 10:25 Joseph Lo
[not found] ` <1351506345-32524-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Joseph Lo @ 2012-10-29 10:25 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo
Add L2 cache controller binding into DT for Tegra.
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* remove "L2" label for cache-controller DT binding
---
arch/arm/boot/dts/tegra20.dtsi | 9 +++++++++
arch/arm/boot/dts/tegra30.dtsi | 9 +++++++++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 6934bca..21ca861 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,15 @@
compatible = "nvidia,tegra20";
interrupt-parent = <&intc>;
+ cache-controller@50043000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x50043000 0x1000>;
+ arm,data-latency = <5 5 2>;
+ arm,tag-latency = <4 4 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
timer@50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 81f5df4..568f291 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,15 @@
compatible = "nvidia,tegra30";
interrupt-parent = <&intc>;
+ cache-controller@50043000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x50043000 0x1000>;
+ arm,data-latency = <6 6 2>;
+ arm,tag-latency = <5 5 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
timer@50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH V2 1/2] ARM: tegra: dt: add L2 cache controller
[not found] ` <1351506345-32524-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
@ 2012-10-29 17:23 ` Stephen Warren
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Warren @ 2012-10-29 17:23 UTC (permalink / raw)
To: Joseph Lo
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 10/29/2012 04:25 AM, Joseph Lo wrote:
> Add L2 cache controller binding into DT for Tegra.
The series applied to Tegra's tree for 3.8. Thanks.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2012-10-29 10:25 [PATCH V2 1/2] ARM: tegra: dt: add L2 cache controller Joseph Lo
[not found] ` <1351506345-32524-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-10-29 17:23 ` Stephen Warren
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