From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH V2 1/2] ARM: tegra: dt: add L2 cache controller Date: Mon, 29 Oct 2012 11:23:59 -0600 Message-ID: <508EBBAF.6060101@wwwdotorg.org> References: <1351506345-32524-1-git-send-email-josephl@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1351506345-32524-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Joseph Lo Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 10/29/2012 04:25 AM, Joseph Lo wrote: > Add L2 cache controller binding into DT for Tegra. The series applied to Tegra's tree for 3.8. Thanks.