From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Thierry Reding
<thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>,
Mark Zhang <nvmarkzhang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH] ARM: tegra: dynamically calculate pll_d parameters
Date: Mon, 17 Dec 2012 15:01:34 -0700 [thread overview]
Message-ID: <50CF963E.7020506@wwwdotorg.org> (raw)
In-Reply-To: <1355767103-5303-1-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
On 12/17/2012 10:58 AM, Lucas Stach wrote:
> Calculate PLL_D parameters in a dynamically instead of using a fixed
> table. This allows TegraDRM to drive outputs with CVT compliant modes.
Prashant, can you please review this, and comment on the best approach
for dealing with the conflict this has with your clock driver rework.
Thanks.
Lucas, I assume this algorithm generates the same cpcon values (and
indeed M/N/P values) as were in the fixed pll_d_freq_table before?
next prev parent reply other threads:[~2012-12-17 22:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-17 17:58 [PATCH] ARM: tegra: dynamically calculate pll_d parameters Lucas Stach
[not found] ` <1355767103-5303-1-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
2012-12-17 22:01 ` Stephen Warren [this message]
[not found] ` <50CF963E.7020506-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-12-17 22:16 ` Lucas Stach
2012-12-18 5:45 ` Prashant Gaikwad
2012-12-18 6:58 ` Thierry Reding
[not found] ` <20121218065857.GA5151-RM9K5IK7kjIyiCvfTdI0JKcOhU4Rzj621B7CTYaBSLdn68oJJulU0Q@public.gmane.org>
2012-12-18 8:40 ` Lucas Stach
2012-12-18 8:36 ` Mark Zhang
[not found] ` <50D02B0F.4020307-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2012-12-18 9:19 ` Lucas Stach
2012-12-18 16:40 ` Stephen Warren
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