From: Mark Zhang <nvmarkzhang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Thierry Reding
<thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
Cc: David Airlie <airlied-cv59FeDIM0c@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH v2 2/5] drm/tegra: Add plane support
Date: Tue, 15 Jan 2013 17:53:03 +0800 [thread overview]
Message-ID: <50F526FF.1010101@gmail.com> (raw)
In-Reply-To: <1358179560-26799-3-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
On 01/15/2013 12:05 AM, Thierry Reding wrote:
> Add support for the B and C planes which support RGB and YUV pixel
> formats and can be used as overlays or hardware cursor.
I think "hardware cursor" has specific meaning for Tegra(e.g: Tegra30
has a 32x32 24bpp or 64x64 2bpp hardware cursor). So you may change it
to "hardware accelerated cursor"?
>
> Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
> ---
[...]
> +
> +static const uint32_t plane_formats[] = {
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_YUV422,
I haven't found something related with YUV format in this patch set. For
example, "tegra_dc_format" also doesn't take YUV into consideration. So
remove this line.
> +};
> +
> +static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
> +{
> + unsigned int i;
> + int err = 0;
> +
> + for (i = 0; i < 2; i++) {
> + struct tegra_plane *plane;
> +
> + plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
> + if (!plane)
> + return -ENOMEM;
> +
> + plane->index = i;
I suggest to change this line to: "plane->index = i + 1;". This makes
the plane's index be consistent with Tegra's windows number. And also we
don't need to worry about passing "plane->index + 1" to some functions
which need to know which window is operating on.
> +
> + err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
> + &tegra_plane_funcs, plane_formats,
> + ARRAY_SIZE(plane_formats), false);
> + if (err < 0)
> + return err;
> + }
> +
> + return 0;
> +}
> +
[...]
>
> +int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
> + const struct tegra_dc_window *window)
> +{
> + unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
> + unsigned long value;
> +
> + bpp = window->bits_per_pixel / 8;
> +
> + value = WINDOW_A_SELECT << index;
> + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
> +
> + tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
> + tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
> +
> + value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
> + tegra_dc_writel(dc, value, DC_WIN_POSITION);
> +
> + value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
> + tegra_dc_writel(dc, value, DC_WIN_SIZE);
> +
> + h_offset = window->src.x * bpp;
> + v_offset = window->src.y;
> + h_size = window->src.w * bpp;
> + v_size = window->src.h;
> +
> + value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
> + tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
> +
> + h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
> + v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
> +
> + value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
> + tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
> +
> + h_dda = compute_initial_dda(window->src.x);
> + v_dda = compute_initial_dda(window->src.y);
> +
In current implementation, "compute_initial_dda" always returns zero. So
why we need it? Although according to TRM, typically we set H/V initial
dda to zero.
> + tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
> + tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
> +
> + tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
> + tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
> +
> + tegra_dc_writel(dc, window->base, DC_WINBUF_START_ADDR);
> + tegra_dc_writel(dc, window->stride, DC_WIN_LINE_STRIDE);
> + tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
> + tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
> +
> + value = WIN_ENABLE;
> +
> + if (bpp < 24)
> + value |= COLOR_EXPAND;
> +
> + tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
> +
> + /*
> + * Disable blending and assume Window A is the bottom-most window,
> + * Window C is the top-most window and Window B is in the middle.
> + */
> + tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
> + tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
> +
> + switch (index) {
> + case 0:
> + tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
> + tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
> + tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
> + break;
> +
> + case 1:
> + tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
> + tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
> + tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
> + break;
> +
> + case 2:
> + tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
> + tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
> + tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
> + break;
> + }
> +
> + value = (WIN_A_ACT_REQ << index) | (WIN_A_UPDATE << index);
> + tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
> +
> + return 0;
> +}
> +
> +unsigned int tegra_dc_format(uint32_t format)
> +{
> + switch (format) {
> + case DRM_FORMAT_XRGB8888:
> + return WIN_COLOR_DEPTH_B8G8R8A8;
> +
Just for curious, why we choose "WIN_COLOR_DEPTH_B8G8R8A8" while not
"WIN_COLOR_DEPTH_R8G8B8A8" here? I recall you and Stephen talked about
this last year but I still don't know the reason.
> + case DRM_FORMAT_RGB565:
> + return WIN_COLOR_DEPTH_B5G6R5;
> +
> + default:
> + break;
> + }
> +
> + WARN(1, "unsupported pixel format %u, using default\n", format);
> + return WIN_COLOR_DEPTH_B8G8R8A8;
> +}
> +
[...]
> +/* from dc.c */
> +extern unsigned int tegra_dc_format(uint32_t format);
> +extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
> + const struct tegra_dc_window *window);
> +
> struct tegra_output_ops {
> int (*enable)(struct tegra_output *output);
> int (*disable)(struct tegra_output *output);
>
next prev parent reply other threads:[~2013-01-15 9:53 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-14 16:05 [PATCH v2 0/5] drm/tegra: Miscellaneous enhancements Thierry Reding
[not found] ` <1358179560-26799-1-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
2013-01-14 16:05 ` [PATCH v2 1/5] drm: Allow vblank support without DRIVER_HAVE_IRQ Thierry Reding
2013-01-14 16:05 ` [PATCH v2 2/5] drm/tegra: Add plane support Thierry Reding
[not found] ` <1358179560-26799-3-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
2013-01-14 17:03 ` Lucas Stach
2013-01-15 11:19 ` Thierry Reding
2013-01-15 9:53 ` Mark Zhang [this message]
[not found] ` <50F526FF.1010101-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-01-15 10:50 ` Lucas Stach
2013-01-18 3:59 ` Mark Zhang
2013-01-15 11:35 ` Ville Syrjälä
[not found] ` <20130115113532.GC3503-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2013-01-15 11:50 ` Thierry Reding
2013-01-14 16:05 ` [PATCH v2 3/5] drm/tegra: Implement .mode_set_base() Thierry Reding
[not found] ` <1358179560-26799-4-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
2013-01-14 17:14 ` Lucas Stach
2013-01-17 6:10 ` Mark Zhang
2013-01-14 16:05 ` [PATCH v2 4/5] drm/tegra: Implement VBLANK support Thierry Reding
[not found] ` <1358179560-26799-5-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
2013-01-22 17:37 ` Mario Kleiner
[not found] ` <50FECE63.7090009-TdbV1Z3I5XE0NhjG498hmQ@public.gmane.org>
2013-01-22 18:39 ` Lucas Stach
2013-01-22 18:49 ` Jon Mayo
[not found] ` <CADWT_cOjVg9-hB+jWuEUr+Ou-YECBN73WQXNy17qXf3TO1ZjpQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-01-22 19:59 ` Mario Kleiner
[not found] ` <50FEEF92.9060009-TdbV1Z3I5XE0NhjG498hmQ@public.gmane.org>
2013-01-23 8:02 ` Terje Bergström
[not found] ` <50FF990C.3040902-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-11 9:08 ` Thierry Reding
[not found] ` <20130211090840.GB3423-RM9K5IK7kjIQXX3q8xo1gnVAuStQJXxyR5q1nwbD4aMs9pC9oP6+/A@public.gmane.org>
2013-02-11 15:43 ` Terje Bergström
2013-01-22 19:20 ` Mario Kleiner
[not found] ` <50FEE681.7020208-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-01-22 19:27 ` Jon Mayo
[not found] ` <CADWT_cOpSBR+DiKwQ4PvYk8-o88Wf5=Tz+ho_g4MdUVKMtc-dw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-01-22 20:08 ` Mario Kleiner
2013-02-11 9:13 ` Thierry Reding
2013-02-15 22:38 ` Mario Kleiner
2013-01-14 16:06 ` [PATCH v2 5/5] drm/tegra: Implement page-flipping support Thierry Reding
[not found] ` <1358179560-26799-6-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
2013-01-16 11:10 ` Mark Zhang
[not found] ` <50F68AB2.4030408-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-01-16 11:53 ` Lucas Stach
2013-01-17 4:49 ` Mark Zhang
2013-01-17 6:33 ` Mark Zhang
2013-01-22 8:31 ` Terje Bergström
[not found] ` <50FE4E4F.6080506-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-01-22 8:57 ` Thierry Reding
[not found] ` <20130122085756.GA6315-RM9K5IK7kjIyiCvfTdI0JKcOhU4Rzj621B7CTYaBSLdn68oJJulU0Q@public.gmane.org>
2013-01-22 9:15 ` Lucas Stach
2013-01-22 9:31 ` Thierry Reding
[not found] ` <20130122093150.GA22264-RM9K5IK7kjIyiCvfTdI0JKcOhU4Rzj621B7CTYaBSLdn68oJJulU0Q@public.gmane.org>
2013-01-22 9:44 ` Terje Bergström
[not found] ` <50FE5F61.4080103-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-01-22 9:48 ` Lucas Stach
2013-01-22 10:39 ` Terje Bergström
2013-01-22 9:35 ` Terje Bergström
2013-01-22 17:27 ` Mario Kleiner
[not found] ` <50FECBFC.8080307-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-02-11 9:00 ` Thierry Reding
[not found] ` <20130211090001.GA3423-RM9K5IK7kjIQXX3q8xo1gnVAuStQJXxyR5q1nwbD4aMs9pC9oP6+/A@public.gmane.org>
2013-02-15 22:34 ` Mario Kleiner
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