From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH] clk: tegra: initialise parent of uart clocks Date: Wed, 06 Feb 2013 10:37:00 -0700 Message-ID: <511294BC.1020808@wwwdotorg.org> References: <1360147661-5435-1-git-send-email-ldewangan@nvidia.com> <20130206122239.GH3073@tbergstrom-lnx.Nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20130206122239.GH3073-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Peter De Schrijver , Prashant Gaikwad Cc: Laxman Dewangan , Stephen Warren , "mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: linux-tegra@vger.kernel.org On 02/06/2013 05:22 AM, Peter De Schrijver wrote: > On Wed, Feb 06, 2013 at 11:47:41AM +0100, Laxman Dewangan wrote: >> Initialise the parent of UARTs to PLLP and disabling clock by >> default. >> > > I wonder if we should move the parent definitions to DT at some point. I think that's what Prashant is going to work on next, right?