Re: [PATCH 1/1] clk: tegra: Fix periph_clk_to_bit macro

[Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]

On Thursday 07 March 2013 03:29 AM, Stephen Warren wrote:
> On 03/06/2013 02:47 PM, Andrew Chew wrote:
>> The parameter name should be "gate", not "periph".  This worked, however,
>> because it happens that everywhere periph_clk_to_bit is called, "gate" was
>> in the local scope.
> Peter, Prashant, can I get an ack/reviewed-by please?

Thanks for the fix!!

Reviewed-by: Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

> Note: I'm also CC'ing Mike and the LAKML mailing list; common clock
> driver changes should be sent to Mike as CCF maintainer, and any
> ARM-related changes should typically get sent to LAKML in the absence of
> any other specific subsystem list.
>
>> Signed-off-by: Yen Lin <yelin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> Signed-off-by: Andrew Chew <achew-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>>   drivers/clk/tegra/clk-periph-gate.c |    2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
>> index 6dd5332..d87e1ce 100644
>> --- a/drivers/clk/tegra/clk-periph-gate.c
>> +++ b/drivers/clk/tegra/clk-periph-gate.c
>> @@ -41,7 +41,7 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>>   #define write_rst_clr(val, gate) \
>>   	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
>>   
>> -#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
>> +#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
>>   
>>   /* Peripheral gate clock ops */
>>   static int clk_periph_is_enabled(struct clk_hw *hw)
> --
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