From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Subject: Re: [PATCH] clk: tegra: Allow PLLE training to succeed
Date: Fri, 15 Mar 2013 13:28:21 -0600
Message-ID: <51437655.1030008@wwwdotorg.org>
References: <1363274825-2439-1-git-send-email-thierry.reding@avionic-design.de>
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To: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
List-Id: linux-tegra@vger.kernel.org

On 03/14/2013 09:27 AM, Thierry Reding wrote:
> Under some circumstances the PLLE needs to be retrained, in which case
> access to the PMC registers is required. Fix this by passing a pointer
> to the PMC registers instead of NULL when registering the PLLE clock.

Mike, I believe this patch is appropriate as a fix for v3.9. I assume
you'll take it through the clock tree? Thanks.