[PATCH V5 0/9] ARM: tegra: add platform suspend support

[PATCH V5 0/9] ARM: tegra: add platform suspend support

[Joseph Lo]

This series introduces a basic functionality for Tegra to support the
platform suspend and resume.

Note: This series only adds the support for Tegra20 and Tegra30. The
Tegra114 will be supported later.

Verified on Seaboard and Cardhu.

V5:
* some fixes from V4's review comments

V4:
* add tegra_pm_validate_suspend_mode() to validate the suspend mode config
  from DT
* squash the patch below into [4/9] to avoid churn after this series
  [2/3] ARM: tegra: refactor the pmc_pm_set function

V3:
* fix the PMC DT configurations for paz00 board
* add a protection for only support LP2 suspend mode

V2:
* re-order the patch sequence to make sure the suspend function can be
  enabled well after the last patch be merged
* squash the patches that defined the PM bindings for PMC and the
  implementation


Joseph Lo (9):
  gpio: tegra: add gpio wakeup source handling
  ARM: tegra: irq: add wake up handling
  ARM: dt: tegra: add bindings of power management configurations for
    PMC
  ARM: tegra: pm: add platform suspend support
  ARM: dts: tegra: add power gpio keys to DT
  ARM: dts: tegra: whistler: add wakeup source for KBC
  ARM: dts: tegra: add non-removable and keep-power-in-suspend property
    for MMC
  ARM: tegra: config: defconfig update
  ARM: dts: tegra: add the PM configurations of PMC

 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  42 ++++++-
 arch/arm/boot/dts/tegra20-harmony.dts              |  17 +++
 arch/arm/boot/dts/tegra20-paz00.dts                |   7 ++
 arch/arm/boot/dts/tegra20-seaboard.dts             |   8 ++
 arch/arm/boot/dts/tegra20-trimslice.dts            |  20 +++
 arch/arm/boot/dts/tegra20-ventana.dts              |  19 +++
 arch/arm/boot/dts/tegra20-whistler.dts             |  10 ++
 arch/arm/boot/dts/tegra30-beaver.dts               |   8 ++
 arch/arm/boot/dts/tegra30-cardhu-a02.dts           |   1 +
 arch/arm/boot/dts/tegra30-cardhu-a04.dts           |   1 +
 arch/arm/boot/dts/tegra30-cardhu.dtsi              |   8 ++
 arch/arm/configs/tegra_defconfig                   |   1 +
 arch/arm/mach-tegra/common.c                       |   3 +
 arch/arm/mach-tegra/irq.c                          |  96 ++++++++++++++-
 arch/arm/mach-tegra/irq.h                          |   6 +
 arch/arm/mach-tegra/pm.c                           |  93 ++++++++++++--
 arch/arm/mach-tegra/pm.h                           |  15 +++
 arch/arm/mach-tegra/pmc.c                          | 134 ++++++++++++++++++++-
 arch/arm/mach-tegra/pmc.h                          |  12 +-
 drivers/gpio/gpio-tegra.c                          |  21 +++-
 20 files changed, 500 insertions(+), 22 deletions(-)

-- 
1.8.2

[PATCH V5 1/9] gpio: tegra: add gpio wakeup source handling

[Joseph Lo]

This patch add the gpio wakeup source handling for the Tegra platform. It
was be done by enabling the irq for the gpio in the gpio controller and
enabling the bank irq of the gpio in the Tegra legacy irq controller when
the system going to suspend.

Based on the work by:
Varun Wadekar <vwadekar-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Cc: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
V5:
* no change
V4:
* no change
V3:
* no change
V2:
* no change
---
 drivers/gpio/gpio-tegra.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index a78a81f..2f1b265 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -72,6 +72,7 @@ struct tegra_gpio_bank {
 	u32 oe[4];
 	u32 int_enb[4];
 	u32 int_lvl[4];
+	u32 wake_enb[4];
 #endif
 };
 
@@ -333,15 +334,31 @@ static int tegra_gpio_suspend(struct device *dev)
 			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
 			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
 			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
+
+			/* Enable gpio irq for wake up source */
+			tegra_gpio_writel(bank->wake_enb[p],
+					  GPIO_INT_ENB(gpio));
 		}
 	}
 	local_irq_restore(flags);
 	return 0;
 }
 
-static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
+static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 {
 	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+	int gpio = d->hwirq;
+	u32 port, bit, mask;
+
+	port = GPIO_PORT(gpio);
+	bit = GPIO_BIT(gpio);
+	mask = BIT(bit);
+
+	if (enable)
+		bank->wake_enb[port] |= mask;
+	else
+		bank->wake_enb[port] &= ~mask;
+
 	return irq_set_irq_wake(bank->irq, enable);
 }
 #endif
@@ -353,7 +370,7 @@ static struct irq_chip tegra_gpio_irq_chip = {
 	.irq_unmask	= tegra_gpio_irq_unmask,
 	.irq_set_type	= tegra_gpio_irq_set_type,
 #ifdef CONFIG_PM_SLEEP
-	.irq_set_wake	= tegra_gpio_wake_enable,
+	.irq_set_wake	= tegra_gpio_irq_set_wake,
 #endif
 };
 
-- 
1.8.2

Re: [PATCH V5 1/9] gpio: tegra: add gpio wakeup source handling

[Linus Walleij]

On Tue, Apr 2, 2013 at 1:20 PM, Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> This patch ad
d the gpio wakeup source handling for the Tegra platform. It
> was be done by enabling the irq for the gpio in the gpio controller and
> enabling the bank irq of the gpio in the Tegra legacy irq controller when
> the system going to suspend.
>
> Based on the work by:
> Varun Wadekar <vwadekar-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Cc: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
> Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> V5:
> * no change
> V4:
> * no change
> V3:
> * no change
> V2:
> * no change

Shall I just apply this to the GPIO tree to stop these repetitive mails
from coming?

Yours,
Linus Walleij

Re: [PATCH V5 1/9] gpio: tegra: add gpio wakeup source handling

[Stephen Warren]

On 04/03/2013 10:29 AM, Linus Walleij wrote:
> On Tue, Apr 2, 2013 at 1:20 PM, Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> This patch ad
> d the gpio wakeup source handling for the Tegra platform. It
>> was be done by enabling the irq for the gpio in the gpio controller and
>> enabling the bank irq of the gpio in the Tegra legacy irq controller when
>> the system going to suspend.
>>
>> Based on the work by:
>> Varun Wadekar <vwadekar-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> Cc: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
>> Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> ---
>> V5:
>> * no change
>> V4:
>> * no change
>> V3:
>> * no change
>> V2:
>> * no change
> 
> Shall I just apply this to the GPIO tree to stop these repetitive mails
> from coming?

It's part of a series where other patches are being rev'd. I'll apply it
to the Tegra tree with the series once it's final.

Re: [PATCH V5 1/9] gpio: tegra: add gpio wakeup source handling

[Stephen Warren]

On 04/03/2013 10:52 AM, Stephen Warren wrote:
> On 04/03/2013 10:29 AM, Linus Walleij wrote:
>> On Tue, Apr 2, 2013 at 1:20 PM, Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>>> This patch ad
>> d the gpio wakeup source handling for the Tegra platform. It
>>> was be done by enabling the irq for the gpio in the gpio controller and
>>> enabling the bank irq of the gpio in the Tegra legacy irq controller when
>>> the system going to suspend.
>>>
>>> Based on the work by:
>>> Varun Wadekar <vwadekar-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>>
>>> Cc: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
>>> Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>> Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>> ---
>>> V5:
>>> * no change
>>> V4:
>>> * no change
>>> V3:
>>> * no change
>>> V2:
>>> * no change
>>
>> Shall I just apply this to the GPIO tree to stop these repetitive mails
>> from coming?
> 
> It's part of a series where other patches are being rev'd. I'll apply it
> to the Tegra tree with the series once it's final.

By the way, it's checked in now, so there won't be any more versions posted.

I guess I should have just applied this patch in an earlier iteration
since it was ack'd and only later patches in the series needed changes.

[PATCH V5 2/9] ARM: tegra: irq: add wake up handling

[Joseph Lo]

Add the wake up handling for legacy irq controller, and using
IRQCHIP_MASK_ON_SUSPEND for wake irq handling.

Based on the work by:
Varun Wadekar <vwadekar-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V5:
* don't use BUG_ON when irq_nr is not correct in set_wake function
V4:
* no change
V3:
* no change
V2:
* no change
---
 arch/arm/mach-tegra/common.c |  2 +
 arch/arm/mach-tegra/irq.c    | 96 +++++++++++++++++++++++++++++++++++++++++++-
 arch/arm/mach-tegra/irq.h    |  6 +++
 3 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index b02ebe7..c84505c 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
+#include "irq.h"
 #include "pmc.h"
 #include "apbio.h"
 #include "sleep.h"
@@ -64,6 +65,7 @@ void __init tegra_dt_init_irq(void)
 	tegra_pmc_init();
 	tegra_init_irq();
 	irqchip_init();
+	tegra_legacy_irq_syscore_init();
 }
 #endif
 
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1952e82..0de4eed 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -4,7 +4,7 @@
  * Author:
  *	Colin Cross <ccross-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
  *
- * Copyright (C) 2010, NVIDIA Corporation
+ * Copyright (C) 2010,2013, NVIDIA Corporation
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/syscore_ops.h>
 
 #include "board.h"
 #include "iomap.h"
@@ -43,6 +44,7 @@
 #define ICTLR_COP_IEP_CLASS	0x3c
 
 #define FIRST_LEGACY_IRQ 32
+#define TEGRA_MAX_NUM_ICTLRS	5
 
 #define SGI_MASK 0xFFFF
 
@@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = {
 	IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
 
+#ifdef CONFIG_PM_SLEEP
+static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+
 bool tegra_pending_sgi(void)
 {
 	u32 pending_set;
@@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d)
 	return 1;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+	u32 irq = d->irq;
+	u32 index, mask;
+
+	if (irq < FIRST_LEGACY_IRQ ||
+		irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
+		return -EINVAL;
+
+	index = ((irq - FIRST_LEGACY_IRQ) / 32);
+	mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
+	if (enable)
+		ictlr_wake_mask[index] |= mask;
+	else
+		ictlr_wake_mask[index] &= ~mask;
+
+	return 0;
+}
+
+static int tegra_legacy_irq_suspend(void)
+{
+	unsigned long flags;
+	int i;
+
+	local_irq_save(flags);
+	for (i = 0; i < num_ictlrs; i++) {
+		void __iomem *ictlr = ictlr_reg_base[i];
+		/* Save interrupt state */
+		cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
+		cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
+		cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
+		cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
+
+		/* Disable COP interrupts */
+		writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+
+		/* Disable CPU interrupts */
+		writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+
+		/* Enable the wakeup sources of ictlr */
+		writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
+	}
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+static void tegra_legacy_irq_resume(void)
+{
+	unsigned long flags;
+	int i;
+
+	local_irq_save(flags);
+	for (i = 0; i < num_ictlrs; i++) {
+		void __iomem *ictlr = ictlr_reg_base[i];
+		writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
+		writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+		writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
+		writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
+		writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+		writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
+	}
+	local_irq_restore(flags);
+}
+
+static struct syscore_ops tegra_legacy_irq_syscore_ops = {
+	.suspend = tegra_legacy_irq_suspend,
+	.resume = tegra_legacy_irq_resume,
+};
+
+int tegra_legacy_irq_syscore_init(void)
+{
+	register_syscore_ops(&tegra_legacy_irq_syscore_ops);
+
+	return 0;
+}
+#else
+#define tegra_set_wake NULL
+#endif
+
 void __init tegra_init_irq(void)
 {
 	int i;
@@ -150,6 +242,8 @@ void __init tegra_init_irq(void)
 	gic_arch_extn.irq_mask = tegra_mask;
 	gic_arch_extn.irq_unmask = tegra_unmask;
 	gic_arch_extn.irq_retrigger = tegra_retrigger;
+	gic_arch_extn.irq_set_wake = tegra_set_wake;
+	gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
 	/*
 	 * Check if there is a devicetree present, since the GIC will be
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
index 5142649..bc05ce5 100644
--- a/arch/arm/mach-tegra/irq.h
+++ b/arch/arm/mach-tegra/irq.h
@@ -19,4 +19,10 @@
 
 bool tegra_pending_sgi(void);
 
+#ifdef CONFIG_PM_SLEEP
+int tegra_legacy_irq_syscore_init(void);
+#else
+static inline int tegra_legacy_irq_syscore_init(void) { return 0; }
+#endif
+
 #endif
-- 
1.8.2

[PATCH V5 3/9] ARM: dt: tegra: add bindings of power management configurations for PMC

[Joseph Lo]

The PMC mostly controls the entry and exit of the system from different
sleep modes. Different platform or system may have different configurations.
The power management configurations of PMC is represented as some properties.
The system needs to define the properties when the system supports deep sleep
mode (i.e. suspend).

Cc: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V5:
* fix typos
V4:
* no change
V3:
* fix typos
V2:
* squash the patches that defined the PM bindings for PMC and the
  implementation
* replace the "unsigned long" with "u32" for the variables that are parsed
  from DT
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      | 42 ++++++++++-
 arch/arm/mach-tegra/pmc.c                          | 83 ++++++++++++++++++++++
 arch/arm/mach-tegra/pmc.h                          |  8 +++
 3 files changed, 132 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index 1cb8f6b..79b8390 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -1,9 +1,15 @@
 NVIDIA Tegra Power Management Controller (PMC)
 
-Properties:
+The PMC block interacts with an external Power Management Unit. The PMC
+mostly controls the entry and exit of the system from different sleep
+modes. It provides power-gating controllers for SoC and CPU power-islands.
+
+Required properties:
 - name : Should be pmc
 - compatible : Should contain "nvidia,tegra<chip>-pmc".
 - reg : Offset and length of the register set for the device
+
+Optional properties:
 - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
   The PMU is an external Power Management Unit, whose interrupt output
   signal is fed into the PMC. This signal is optionally inverted, and then
@@ -11,6 +17,32 @@ Properties:
   handling of this interrupt signal, merely its inversion.
 - clocks : the source clock of PMC
 - clock-names : the name of source clock of PMC
+- nvidia,suspend-mode : The suspend mode that the platform should use.
+  Valid values are 0, 1 and 2:
+  0 (LP0): CPU + Core voltage off and DRAM in self-refresh
+  1 (LP1): CPU voltage off and DRAM in self-refresh
+  2 (LP2): CPU voltage off
+- nvidia,core-power-req-active-high : Boolean, core power request active-high
+- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
+- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
+- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
+			   is enabled.
+
+Required properties when nvidia,suspend-mode is specified:
+- nvidia,cpu-pwr-good-time : CPU power good time in uS.
+- nvidia,cpu-pwr-off-time : CPU power off time in uS.
+- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
+			      Core power good time in uS.
+- nvidia,core-pwr-off-time : Core power off time in uS.
+
+Required properties when nvidia,suspend-mode=<0>:
+- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
+  The LP0 vector contains the warm boot code that is executed by AVP when
+  resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
+  processor and always being the first boot processor when chip is power on
+  or resume from deep sleep mode. When the system is resumed from the deep
+  sleep mode, the warm boot code will restore some PLLs, clocks and then
+  bring up CPU0 for resuming the system.
 
 Example:
 
@@ -21,6 +53,14 @@ pmc@7000f400 {
 	nvidia,invert-interrupt;
 	clocks = <&tegra_car 110>, <&clk32k_in>;
 	clock-names = "pclk", "clk32k_in";
+	nvidia,suspend-mode = <1>;
+	nvidia,cpu-pwr-good-time = <2000>;
+	nvidia,cpu-pwr-off-time = <100>;
+	nvidia,core-pwr-good-time = <3845 3845>;
+	nvidia,core-pwr-off-time = <458>;
+	nvidia,core-power-req-active-high;
+	nvidia,sys-clock-req-active-high;
+	nvidia,lp0-vec = <0xbdffd000 0x2000>;
 };
 
 / Tegra board dts file
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 8abf02f..5323bca 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -21,6 +21,8 @@
 #include <linux/of_address.h>
 #include <linux/clk.h>
 
+#include "pmc.h"
+
 #define PMC_CTRL			0x0
 #define PMC_CTRL_INTR_LOW		(1 << 17)
 #define PMC_PWRGATE_TOGGLE		0x30
@@ -49,6 +51,22 @@ static void __iomem *tegra_pmc_base;
 static bool tegra_pmc_invert_interrupt;
 static struct clk *tegra_pclk;
 
+struct pmc_pm_data {
+	u32 cpu_good_time;	/* CPU power good time in uS */
+	u32 cpu_off_time;	/* CPU power off time in uS */
+	u32 core_osc_time;	/* Core power good osc time in uS */
+	u32 core_pmu_time;	/* Core power good pmu time in uS */
+	u32 core_off_time;	/* Core power off time in uS */
+	bool corereq_high;	/* Core power request active-high */
+	bool sysclkreq_high;	/* System clock request active-high */
+	bool combined_req;	/* Combined pwr req for CPU & Core */
+	bool cpu_pwr_good_en;	/* CPU power good signal is enabled */
+	u32 lp0_vec_phy_addr;	/* The phy addr of LP0 warm boot code */
+	u32 lp0_vec_size;	/* The size of LP0 warm boot code */
+	enum tegra_suspend_mode suspend_mode;
+};
+static struct pmc_pm_data pmc_pm_data;
+
 static inline u32 tegra_pmc_readl(u32 reg)
 {
 	return readl(tegra_pmc_base + reg);
@@ -177,6 +195,10 @@ static const struct of_device_id matches[] __initconst = {
 static void tegra_pmc_parse_dt(void)
 {
 	struct device_node *np;
+	u32 prop;
+	enum tegra_suspend_mode suspend_mode;
+	u32 core_good_time[2] = {0, 0};
+	u32 lp0_vec[2] = {0, 0};
 
 	np = of_find_matching_node(NULL, matches);
 	BUG_ON(!np);
@@ -187,6 +209,67 @@ static void tegra_pmc_parse_dt(void)
 				     "nvidia,invert-interrupt");
 	tegra_pclk = of_clk_get_by_name(np, "pclk");
 	WARN_ON(IS_ERR(tegra_pclk));
+
+	/* Grabbing the power management configurations */
+	if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
+		suspend_mode = TEGRA_SUSPEND_NONE;
+	} else {
+		switch (prop) {
+		case 0:
+			suspend_mode = TEGRA_SUSPEND_LP0;
+			break;
+		case 1:
+			suspend_mode = TEGRA_SUSPEND_LP1;
+			break;
+		case 2:
+			suspend_mode = TEGRA_SUSPEND_LP2;
+			break;
+		default:
+			suspend_mode = TEGRA_SUSPEND_NONE;
+			break;
+		}
+	}
+
+	if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
+		suspend_mode = TEGRA_SUSPEND_NONE;
+	pmc_pm_data.cpu_good_time = prop;
+
+	if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
+		suspend_mode = TEGRA_SUSPEND_NONE;
+	pmc_pm_data.cpu_off_time = prop;
+
+	if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
+			core_good_time, ARRAY_SIZE(core_good_time)))
+		suspend_mode = TEGRA_SUSPEND_NONE;
+	pmc_pm_data.core_osc_time = core_good_time[0];
+	pmc_pm_data.core_pmu_time = core_good_time[1];
+
+	if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
+				 &prop))
+		suspend_mode = TEGRA_SUSPEND_NONE;
+	pmc_pm_data.core_off_time = prop;
+
+	pmc_pm_data.corereq_high = of_property_read_bool(np,
+				"nvidia,core-power-req-active-high");
+
+	pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
+				"nvidia,sys-clock-req-active-high");
+
+	pmc_pm_data.combined_req = of_property_read_bool(np,
+				"nvidia,combined-power-req");
+
+	pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
+				"nvidia,cpu-pwr-good-en");
+
+	if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
+				       ARRAY_SIZE(lp0_vec)))
+		if (suspend_mode == TEGRA_SUSPEND_LP0)
+			suspend_mode = TEGRA_SUSPEND_LP1;
+
+	pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
+	pmc_pm_data.lp0_vec_size = lp0_vec[1];
+
+	pmc_pm_data.suspend_mode = suspend_mode;
 }
 
 void __init tegra_pmc_init(void)
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 22f16c9..6bc0fc09 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,14 @@
 #ifndef __MACH_TEGRA_PMC_H
 #define __MACH_TEGRA_PMC_H
 
+enum tegra_suspend_mode {
+	TEGRA_SUSPEND_NONE = 0,
+	TEGRA_SUSPEND_LP2,	/* CPU voltage off */
+	TEGRA_SUSPEND_LP1,	/* CPU voltage off, DRAM self-refresh */
+	TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
+	TEGRA_MAX_SUSPEND_MODE,
+};
+
 #ifdef CONFIG_PM_SLEEP
 void set_power_timers(unsigned long us_on, unsigned long us_off);
 #endif
-- 
1.8.2

[PATCH V5 4/9] ARM: tegra: pm: add platform suspend support

[Joseph Lo]

Adding suspend to RAM support for Tegra platform. There are three suspend
mode for Tegra. The difference were below.

* LP2: CPU voltage off
* LP1: CPU voltage off, DRAM in self-refresh
* LP0: CPU + Core voltage off, DRAM in self-refresh

After this patch, the LP2 suspend mode will be supported.

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V5:
* move tegra_init_suspend() to tegra_init_late()
* remove useless BUG_ON for the polarity of CPU power request
V4:
* add tegra_pm_validate_suspend_mode() to validate the suspend mode config
  from DT
* squash the patch below that origianl being introduced after this series
  to clean up some PM related code
  [2/3] ARM: tegra: refactor the pmc_pm_set function
V3:
* add a protection for only support LP2 suspend mode
V2:
* add the PM_SLEEP protection for "tegra_init_suspend"
* remove "tegra_suspend_{enter/exit}_lp2"
* refactor the "tegra_pmc_pm_set" for non-used parameter
* replace "unsigned long" with "u32" for tegra_pmc_get_cpu_time
---
 arch/arm/mach-tegra/common.c |  1 +
 arch/arm/mach-tegra/pm.c     | 93 +++++++++++++++++++++++++++++++++++++-------
 arch/arm/mach-tegra/pm.h     | 15 +++++++
 arch/arm/mach-tegra/pmc.c    | 51 ++++++++++++++++++++++--
 arch/arm/mach-tegra/pmc.h    |  4 +-
 5 files changed, 146 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index c84505c..eb1f3c8 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -109,5 +109,6 @@ void __init tegra_init_early(void)
 
 void __init tegra_init_late(void)
 {
+	tegra_init_suspend();
 	tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index ef12c0d..14957ff 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -22,6 +22,7 @@
 #include <linux/cpumask.h>
 #include <linux/delay.h>
 #include <linux/cpu_pm.h>
+#include <linux/suspend.h>
 #include <linux/err.h>
 #include <linux/clk/tegra.h>
 
@@ -38,14 +39,10 @@
 #include "fuse.h"
 #include "pmc.h"
 #include "sleep.h"
-
-#define TEGRA_POWER_CPU_PWRREQ_OE	(1 << 16)  /* CPU pwr req enable */
-
-#define PMC_CTRL		0x0
+#include "pmc.h"
 
 #ifdef CONFIG_PM_SLEEP
 static DEFINE_SPINLOCK(tegra_lp2_lock);
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
 void (*tegra_tear_down_cpu)(void);
 
 /*
@@ -140,14 +137,7 @@ static int tegra_sleep_cpu(unsigned long v2p)
 
 void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
 {
-	u32 mode;
-
-	/* Only the last cpu down does the final suspend steps */
-	mode = readl(pmc + PMC_CTRL);
-	mode |= TEGRA_POWER_CPU_PWRREQ_OE;
-	writel(mode, pmc + PMC_CTRL);
-
-	set_power_timers(cpu_on_time, cpu_off_time);
+	tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
 
 	cpu_cluster_pm_enter();
 	suspend_cpu_complex();
@@ -157,4 +147,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
 	restore_cpu_complex();
 	cpu_cluster_pm_exit();
 }
+
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+				enum tegra_suspend_mode mode)
+{
+	/* Tegra114 didn't support any suspending mode yet. */
+	if (tegra_chip_id == TEGRA114)
+		return TEGRA_SUSPEND_NONE;
+
+	/*
+	 * The Tegra devices only support suspending to LP2 currently.
+	 */
+	if (mode > TEGRA_SUSPEND_LP2)
+		return TEGRA_SUSPEND_LP2;
+
+	return mode;
+}
+
+static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
+	[TEGRA_SUSPEND_NONE] = "none",
+	[TEGRA_SUSPEND_LP2] = "LP2",
+	[TEGRA_SUSPEND_LP1] = "LP1",
+	[TEGRA_SUSPEND_LP0] = "LP0",
+};
+
+static int __cpuinit tegra_suspend_enter(suspend_state_t state)
+{
+	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
+
+	if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
+		    mode >= TEGRA_MAX_SUSPEND_MODE))
+		return -EINVAL;
+
+	pr_info("Entering suspend state %s\n", lp_state[mode]);
+
+	tegra_pmc_pm_set(mode);
+
+	local_fiq_disable();
+
+	suspend_cpu_complex();
+	switch (mode) {
+	case TEGRA_SUSPEND_LP2:
+		tegra_set_cpu_in_lp2(0);
+		break;
+	default:
+		break;
+	}
+
+	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+
+	switch (mode) {
+	case TEGRA_SUSPEND_LP2:
+		tegra_clear_cpu_in_lp2(0);
+		break;
+	default:
+		break;
+	}
+	restore_cpu_complex();
+
+	local_fiq_enable();
+
+	return 0;
+}
+
+static const struct platform_suspend_ops tegra_suspend_ops = {
+	.valid		= suspend_valid_only_mem,
+	.enter		= tegra_suspend_enter,
+};
+
+void __init tegra_init_suspend(void)
+{
+	if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
+		return;
+
+	tegra_pmc_suspend_init();
+
+	suspend_set_ops(&tegra_suspend_ops);
+}
 #endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 787335c..73a45f1 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -21,6 +21,8 @@
 #ifndef _MACH_TEGRA_PM_H_
 #define _MACH_TEGRA_PM_H_
 
+#include "pmc.h"
+
 extern unsigned long l2x0_saved_regs_addr;
 
 void save_cpu_arch_register(void);
@@ -32,4 +34,17 @@ bool tegra_set_cpu_in_lp2(int phy_cpu_id);
 void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
 extern void (*tegra_tear_down_cpu)(void);
 
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+				enum tegra_suspend_mode mode);
+void tegra_init_suspend(void);
+#else
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+				enum tegra_suspend_mode mode)
+{
+	return TEGRA_SUSPEND_NONE;
+}
+static inline void tegra_init_suspend(void) {}
+#endif
+
 #endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 5323bca..0d50d34 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -21,7 +21,14 @@
 #include <linux/of_address.h>
 #include <linux/clk.h>
 
+#include "fuse.h"
+#include "pm.h"
 #include "pmc.h"
+#include "sleep.h"
+
+#define TEGRA_POWER_EFFECT_LP0		(1 << 14)  /* LP0 when CPU pwr gated */
+#define TEGRA_POWER_CPU_PWRREQ_POLARITY	(1 << 15)  /* CPU pwr req polarity */
+#define TEGRA_POWER_CPU_PWRREQ_OE	(1 << 16)  /* CPU pwr req enable */
 
 #define PMC_CTRL			0x0
 #define PMC_CTRL_INTR_LOW		(1 << 17)
@@ -157,15 +164,12 @@ int tegra_pmc_cpu_remove_clamping(int cpuid)
 }
 
 #ifdef CONFIG_PM_SLEEP
-void set_power_timers(unsigned long us_on, unsigned long us_off)
+static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
 {
 	unsigned long long ticks;
 	unsigned long long pclk;
-	unsigned long rate;
 	static unsigned long tegra_last_pclk;
 
-	rate = clk_get_rate(tegra_pclk);
-
 	if (WARN_ON_ONCE(rate <= 0))
 		pclk = 100000000;
 	else
@@ -183,6 +187,44 @@ void set_power_timers(unsigned long us_on, unsigned long us_off)
 	}
 	tegra_last_pclk = pclk;
 }
+
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
+{
+	return pmc_pm_data.suspend_mode;
+}
+
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
+{
+	u32 reg;
+	unsigned long rate = 0;
+
+	reg = tegra_pmc_readl(PMC_CTRL);
+	reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+	reg &= ~TEGRA_POWER_EFFECT_LP0;
+
+	switch (mode) {
+	case TEGRA_SUSPEND_LP2:
+		rate = clk_get_rate(tegra_pclk);
+		break;
+	default:
+		break;
+	}
+
+	set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
+			 rate);
+
+	tegra_pmc_writel(reg, PMC_CTRL);
+}
+
+void tegra_pmc_suspend_init(void)
+{
+	u32 reg;
+
+	/* Always enable CPU power request */
+	reg = tegra_pmc_readl(PMC_CTRL);
+	reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+	tegra_pmc_writel(reg, PMC_CTRL);
+}
 #endif
 
 static const struct of_device_id matches[] __initconst = {
@@ -229,6 +271,7 @@ static void tegra_pmc_parse_dt(void)
 			break;
 		}
 	}
+	suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
 
 	if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
 		suspend_mode = TEGRA_SUSPEND_NONE;
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 6bc0fc09..e1c2df2 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -27,7 +27,9 @@ enum tegra_suspend_mode {
 };
 
 #ifdef CONFIG_PM_SLEEP
-void set_power_timers(unsigned long us_on, unsigned long us_off);
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
+void tegra_pmc_suspend_init(void);
 #endif
 
 bool tegra_pmc_cpu_is_powered(int cpuid);
-- 
1.8.2

[PATCH V5 5/9] ARM: dts: tegra: add power gpio keys to DT

[Joseph Lo]

This adds the power gpio key to DT and enable the wakeup of the gpio key
for the device. The Seaboard and paz00 already had the power gpio key
binding and the power key of Whistler was on KBC. So these boards' device
tree didn't include in this patch.

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V5:
* no change
V4:
* no change
V3:
* no change
V2:
* no change
---
 arch/arm/boot/dts/tegra20-harmony.dts   | 11 +++++++++++
 arch/arm/boot/dts/tegra20-trimslice.dts | 11 +++++++++++
 arch/arm/boot/dts/tegra20-ventana.dts   | 11 +++++++++++
 3 files changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 6e6899a..4f08521 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -581,6 +581,17 @@
 				0x1F0400D6>;	/* KEY_QUESTION */
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			linux,code = <116>; /* KEY_POWER */
+			gpio-key,wakeup;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index b265ebd..8e8d4f6 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -348,6 +348,17 @@
 		gpios = <&gpio 191 1>; /* gpio PX7, active low */
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio 190 1>; /* gpio PX6, active low */
+			linux,code = <116>; /* KEY_POWER */
+			gpio-key,wakeup;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 157a2cd..112ef5c 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -544,6 +544,17 @@
 		bus-width = <8>;
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio 170 1>; /* gpio PV2, active low */
+			linux,code = <116>; /* KEY_POWER */
+			gpio-key,wakeup;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
-- 
1.8.2

[PATCH V5 6/9] ARM: dts: tegra: whistler: add wakeup source for KBC

[Joseph Lo]

Adding KBC as a wakeup source for Whistler board.

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V5:
* no change
V4:
* no change
V3:
* no change
V2:
* no change
---
 arch/arm/boot/dts/tegra20-whistler.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 87632df..0b04262 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -539,6 +539,7 @@
 		nvidia,repeat-delay-ms = <160>;
 		nvidia,kbc-row-pins = <0 1 2>;
 		nvidia,kbc-col-pins = <16 17>;
+		nvidia,wakeup-source;
 		linux,keymap = <0x00000074	/* KEY_POWER */
 				0x01000066	/* KEY_HOME */
 				0x0101009E	/* KEY_BACK */
-- 
1.8.2

[PATCH V5 7/9] ARM: dts: tegra: add non-removable and keep-power-in-suspend property for MMC

[Joseph Lo]

This patch adds "non-removable" property of MMC host where the eMMC device
is for Tegra platform.

And the "keep-power-in-suspend" property was used for the SDIO device that
need this to go into suspend mode (e.g. BRCM43xx series).

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V5:
* no change
V4:
* no change
V3:
* no change
V2:
* no change
---
 arch/arm/boot/dts/tegra20-paz00.dts      | 1 +
 arch/arm/boot/dts/tegra20-seaboard.dts   | 2 ++
 arch/arm/boot/dts/tegra20-ventana.dts    | 2 ++
 arch/arm/boot/dts/tegra20-whistler.dts   | 1 +
 arch/arm/boot/dts/tegra30-beaver.dts     | 1 +
 arch/arm/boot/dts/tegra30-cardhu-a02.dts | 1 +
 arch/arm/boot/dts/tegra30-cardhu-a04.dts | 1 +
 arch/arm/boot/dts/tegra30-cardhu.dtsi    | 1 +
 8 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 54b05b2..c55e062 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -458,6 +458,7 @@
 	sdhci@c8000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
 	};
 
 	gpio-keys {
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 3b347b8..5572ee7 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -593,6 +593,7 @@
 		status = "okay";
 		power-gpios = <&gpio 86 0>; /* gpio PK6 */
 		bus-width = <4>;
+		keep-power-in-suspend;
 	};
 
 	sdhci@c8000400 {
@@ -606,6 +607,7 @@
 	sdhci@c8000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
 	};
 
 	gpio-keys {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 112ef5c..4363764 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -529,6 +529,7 @@
 		status = "okay";
 		power-gpios = <&gpio 86 0>; /* gpio PK6 */
 		bus-width = <4>;
+		keep-power-in-suspend;
 	};
 
 	sdhci@c8000400 {
@@ -542,6 +543,7 @@
 	sdhci@c8000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
 	};
 
 	gpio-keys {
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 0b04262..878790e 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -531,6 +531,7 @@
 	sdhci@c8000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
 	};
 
 	kbc {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index c3e0f25..772e6cf 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -279,6 +279,7 @@
 	sdhci@78000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
 	};
 
 	regulators {
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index adc88aa..e392bd2 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -88,6 +88,7 @@
 		status = "okay";
 		power-gpios = <&gpio 28 0>; /* gpio PD4 */
 		bus-width = <4>;
+		keep-power-in-suspend;
 	};
 };
 
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index 08163e1..d0db6c7 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -100,5 +100,6 @@
 		status = "okay";
 		power-gpios = <&gpio 27 0>; /* gpio PD3 */
 		bus-width = <4>;
+		keep-power-in-suspend;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index eeea511..053913f 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -333,6 +333,7 @@
 	sdhci@78000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
 	};
 
 	regulators {
-- 
1.8.2

Re: [PATCH V5 7/9] ARM: dts: tegra: add non-removable and keep-power-in-suspend property for MMC

[Stephen Warren]

On 04/02/2013 05:20 AM, Joseph Lo wrote:
> This patch adds "non-removable" property of MMC host where the eMMC device
> is for Tegra platform.
> 
> And the "keep-power-in-suspend" property was used for the SDIO device that
> need this to go into suspend mode (e.g. BRCM43xx series).

>  arch/arm/boot/dts/tegra20-paz00.dts      | 1 +
>  arch/arm/boot/dts/tegra20-seaboard.dts   | 2 ++
>  arch/arm/boot/dts/tegra20-ventana.dts    | 2 ++
>  arch/arm/boot/dts/tegra20-whistler.dts   | 1 +
>  arch/arm/boot/dts/tegra30-beaver.dts     | 1 +
>  arch/arm/boot/dts/tegra30-cardhu-a02.dts | 1 +
>  arch/arm/boot/dts/tegra30-cardhu-a04.dts | 1 +
>  arch/arm/boot/dts/tegra30-cardhu.dtsi    | 1 +

I think there are a bunch of other boards that need a similar change,
right? There are certainly eMMC devices on other boards, and shouldn't
they be marked with non-removable? In particular, Beaver, Dalmore, and
Pluto, and likely some/all of the Colibri and Avionic Design boards. I
think it should be obvious which SDHCI devices need this, since there
won't be any cd-gpios property and the bus-width will likely be 8.

Re: [PATCH V5 7/9] ARM: dts: tegra: add non-removable and keep-power-in-suspend property for MMC

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1585 bytes --]

On Tue, Apr 02, 2013 at 01:58:41PM -0600, Stephen Warren wrote:
> On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > This patch adds "non-removable" property of MMC host where the eMMC device
> > is for Tegra platform.
> > 
> > And the "keep-power-in-suspend" property was used for the SDIO device that
> > need this to go into suspend mode (e.g. BRCM43xx series).
> 
> >  arch/arm/boot/dts/tegra20-paz00.dts      | 1 +
> >  arch/arm/boot/dts/tegra20-seaboard.dts   | 2 ++
> >  arch/arm/boot/dts/tegra20-ventana.dts    | 2 ++
> >  arch/arm/boot/dts/tegra20-whistler.dts   | 1 +
> >  arch/arm/boot/dts/tegra30-beaver.dts     | 1 +
> >  arch/arm/boot/dts/tegra30-cardhu-a02.dts | 1 +
> >  arch/arm/boot/dts/tegra30-cardhu-a04.dts | 1 +
> >  arch/arm/boot/dts/tegra30-cardhu.dtsi    | 1 +
> 
> I think there are a bunch of other boards that need a similar change,
> right? There are certainly eMMC devices on other boards, and shouldn't
> they be marked with non-removable? In particular, Beaver, Dalmore, and
> Pluto, and likely some/all of the Colibri and Avionic Design boards. I
> think it should be obvious which SDHCI devices need this, since there
> won't be any cd-gpios property and the bus-width will likely be 8.

For Tegra20 Tamonten we don't use eMMC. Ideally we'd be using NAND to
boot from but that doesn't have mainline support. I have a semi-working
patch and will probably spend some more time getting it ready. The MMC
cards are all removable, though I guess since they are the boot device
they still should remain powered in suspend?

Thierry

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCH V5 7/9] ARM: dts: tegra: add non-removable and keep-power-in-suspend property for MMC

[Joseph Lo]

On Wed, 2013-04-03 at 13:45 +0800, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Tue, Apr 02, 2013 at 01:58:41PM -0600, Stephen Warren wrote:
> > On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > > This patch adds "non-removable" property of MMC host where the eMMC device
> > > is for Tegra platform.
> > > 
> > > And the "keep-power-in-suspend" property was used for the SDIO device that
> > > need this to go into suspend mode (e.g. BRCM43xx series).
> > 
> > >  arch/arm/boot/dts/tegra20-paz00.dts      | 1 +
> > >  arch/arm/boot/dts/tegra20-seaboard.dts   | 2 ++
> > >  arch/arm/boot/dts/tegra20-ventana.dts    | 2 ++
> > >  arch/arm/boot/dts/tegra20-whistler.dts   | 1 +
> > >  arch/arm/boot/dts/tegra30-beaver.dts     | 1 +
> > >  arch/arm/boot/dts/tegra30-cardhu-a02.dts | 1 +
> > >  arch/arm/boot/dts/tegra30-cardhu-a04.dts | 1 +
> > >  arch/arm/boot/dts/tegra30-cardhu.dtsi    | 1 +
> > 
> > I think there are a bunch of other boards that need a similar change,
> > right? There are certainly eMMC devices on other boards, and shouldn't
> > they be marked with non-removable? In particular, Beaver, Dalmore, and
> > Pluto, and likely some/all of the Colibri and Avionic Design boards. I
> > think it should be obvious which SDHCI devices need this, since there
> > won't be any cd-gpios property and the bus-width will likely be 8.
> 
> For Tegra20 Tamonten we don't use eMMC. Ideally we'd be using NAND to
> boot from but that doesn't have mainline support. I have a semi-working
> patch and will probably spend some more time getting it ready. The MMC
> cards are all removable, though I guess since they are the boot device
> they still should remain powered in suspend?
> 
The "non-removable" property is a specific property to avoid the risk of
writing back data to a different card after resume. If you just want to
test the suspend function, you can add "mmc_core.removable=0" in your
boot arg.

The "keep-power-in-suspend" is used for the BRCM43xx series SDIO device.
Without this, it can't go into suspend mode.

Re: [PATCH V5 7/9] ARM: dts: tegra: add non-removable and keep-power-in-suspend property for MMC

[Joseph Lo]

On Wed, 2013-04-03 at 03:58 +0800, Stephen Warren wrote:
> On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > This patch adds "non-removable" property of MMC host where the eMMC device
> > is for Tegra platform.
> > 
> > And the "keep-power-in-suspend" property was used for the SDIO device that
> > need this to go into suspend mode (e.g. BRCM43xx series).
> 
> >  arch/arm/boot/dts/tegra20-paz00.dts      | 1 +
> >  arch/arm/boot/dts/tegra20-seaboard.dts   | 2 ++
> >  arch/arm/boot/dts/tegra20-ventana.dts    | 2 ++
> >  arch/arm/boot/dts/tegra20-whistler.dts   | 1 +
> >  arch/arm/boot/dts/tegra30-beaver.dts     | 1 +
> >  arch/arm/boot/dts/tegra30-cardhu-a02.dts | 1 +
> >  arch/arm/boot/dts/tegra30-cardhu-a04.dts | 1 +
> >  arch/arm/boot/dts/tegra30-cardhu.dtsi    | 1 +
> 
> I think there are a bunch of other boards that need a similar change,
> right? There are certainly eMMC devices on other boards, and shouldn't
> they be marked with non-removable? In particular, Beaver, Dalmore, and
> Pluto, and likely some/all of the Colibri and Avionic Design boards. I
> think it should be obvious which SDHCI devices need this, since there
> won't be any cd-gpios property and the bus-width will likely be 8.

OK, I already added the property for Beaver. I will add one more support
for Dalmore in this patch. For Pluto, it didn't add any SDCHI node in DT
yet. We need another patch to enable SDHCI on Pluto first and add the
properties there.

Thanks,
Joseph

[PATCH V5 8/9] ARM: tegra: config: defconfig update

[Joseph Lo]

KEYBOARD_GPIO:
* Enable gpio-key driver

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V5:
* no change
V4:
* no change
V3:
* no change
V2:
* no change
---
 arch/arm/configs/tegra_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 2b42a2c..a5f0485 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -106,6 +106,7 @@ CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_TEGRA=y
+CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 # CONFIG_LEGACY_PTYS is not set
-- 
1.8.2

[PATCH V5 9/9] ARM: dts: tegra: add the PM configurations of PMC

[Joseph Lo]

Adding the PM configuration of PMC when the platform support suspend
function.

Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V5:
* no change
V4:
* no change
V3:
* fix the configuration for paz00 board
V2:
* no change
---
 arch/arm/boot/dts/tegra20-harmony.dts   | 6 ++++++
 arch/arm/boot/dts/tegra20-paz00.dts     | 6 ++++++
 arch/arm/boot/dts/tegra20-seaboard.dts  | 6 ++++++
 arch/arm/boot/dts/tegra20-trimslice.dts | 9 +++++++++
 arch/arm/boot/dts/tegra20-ventana.dts   | 6 ++++++
 arch/arm/boot/dts/tegra20-whistler.dts  | 8 ++++++++
 arch/arm/boot/dts/tegra30-beaver.dts    | 7 +++++++
 arch/arm/boot/dts/tegra30-cardhu.dtsi   | 7 +++++++
 8 files changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 4f08521..7904eb4 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -429,6 +429,12 @@
 
 	pmc {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <5000>;
+		nvidia,cpu-pwr-off-time = <5000>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <3875>;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	usb@c5000000 {
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index c55e062..680eeeb 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -428,6 +428,12 @@
 
 	pmc {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <2000>;
+		nvidia,cpu-pwr-off-time = <0>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <0>;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	usb@c5000000 {
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 5572ee7..2ff92c9 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -530,6 +530,12 @@
 
 	pmc {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <5000>;
+		nvidia,cpu-pwr-off-time = <5000>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <3875>;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	memory-controller@7000f400 {
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 8e8d4f6..7760b67 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -313,6 +313,15 @@
 		};
 	};
 
+	pmc {
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <5000>;
+		nvidia,cpu-pwr-off-time = <5000>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <3875>;
+		nvidia,sys-clock-req-active-high;
+	};
+
 	usb@c5000000 {
 		status = "okay";
 		nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 4363764..98a1eae 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -506,6 +506,12 @@
 
 	pmc {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <2000>;
+		nvidia,cpu-pwr-off-time = <100>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <458>;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	usb@c5000000 {
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 878790e..ff74be7 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -509,6 +509,14 @@
 
 	pmc {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <2000>;
+		nvidia,cpu-pwr-off-time = <1000>;
+		nvidia,core-pwr-good-time = <0 3845>;
+		nvidia,core-pwr-off-time = <93727>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
+		nvidia,combined-power-req;
 	};
 
 	usb@c5000000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 772e6cf..f17deb0 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -266,6 +266,13 @@
 	pmc {
 		status = "okay";
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <2000>;
+		nvidia,cpu-pwr-off-time = <200>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <0>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	sdhci@78000000 {
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 053913f..9171834 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -320,6 +320,13 @@
 	pmc {
 		status = "okay";
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <2000>;
+		nvidia,cpu-pwr-off-time = <200>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <0>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	sdhci@78000000 {
-- 
1.8.2

Re: [PATCH V5 9/9] ARM: dts: tegra: add the PM configurations of PMC

[Stephen Warren]

On 04/02/2013 05:20 AM, Joseph Lo wrote:
> Adding the PM configuration of PMC when the platform support suspend
> function.

For this patch, some more boards could be supported, but I think we'll
have to rely on other people (Lucas, Thierry) to send patches for them,
since they know the details of the board. It's fine to leave suspend
disabled on those boards until later.

Aside from the 1 other comment I made on this series, I think it's good
to go once your previous 3-long series is fixed and reposted per my
comments on it.

Re: [PATCH V5 9/9] ARM: dts: tegra: add the PM configurations of PMC

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1160 bytes --]

On Tue, Apr 02, 2013 at 02:00:55PM -0600, Stephen Warren wrote:
> On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > Adding the PM configuration of PMC when the platform support suspend
> > function.
> 
> For this patch, some more boards could be supported, but I think we'll
> have to rely on other people (Lucas, Thierry) to send patches for them,
> since they know the details of the board. It's fine to leave suspend
> disabled on those boards until later.

I'm not sure what would be the best way to get the Tamonten devices out
of suspend again. For Plutux and TEC we have a power button that could
possibly be reused. There's a WAKEUP pin on the Tamonten connector which
goes to GPIO PV2, but the mechanism to trigger it is carrier-board
dependent.

For the Medcom-Wide we don't have a power button, but it could possibly
use the WAKEUP pin if that's connected. It seems like in all designs it
goes to the CPLD, but I need to check with engineering if there's a way
to manipulate it.

So yes, I think for now we can leave suspend disabled on Tamonten and I
can send patches to enable it once I've clarified with engineering.

Thierry

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCH V5 9/9] ARM: dts: tegra: add the PM configurations of PMC

[Joseph Lo]

On Wed, 2013-04-03 at 13:59 +0800, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Tue, Apr 02, 2013 at 02:00:55PM -0600, Stephen Warren wrote:
> > On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > > Adding the PM configuration of PMC when the platform support suspend
> > > function.
> > 
> > For this patch, some more boards could be supported, but I think we'll
> > have to rely on other people (Lucas, Thierry) to send patches for them,
> > since they know the details of the board. It's fine to leave suspend
> > disabled on those boards until later.
> 
> I'm not sure what would be the best way to get the Tamonten devices out
> of suspend again. For Plutux and TEC we have a power button that could
> possibly be reused. There's a WAKEUP pin on the Tamonten connector which
> goes to GPIO PV2, but the mechanism to trigger it is carrier-board
> dependent.
> 
> For the Medcom-Wide we don't have a power button, but it could possibly
> use the WAKEUP pin if that's connected. It seems like in all designs it
> goes to the CPLD, but I need to check with engineering if there's a way
> to manipulate it.
> 
> So yes, I think for now we can leave suspend disabled on Tamonten and I
> can send patches to enable it once I've clarified with engineering.
> 
Hi Thierry,

I just recall I still need at least "nvidia,cpu-pwr-good-time" and
"nvidia,cpu-pwr-off-time" two properties to make CPU idle power-down
mode (same with LP2) work normally after this series.

So can you provide me that or point me out where is your downstream
kernel source? There data would be come from DT after this series.

Thanks,
Joseph

Re: [PATCH V5 9/9] ARM: dts: tegra: add the PM configurations of PMC

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2228 bytes --]

On Wed, Apr 03, 2013 at 02:34:25PM +0800, Joseph Lo wrote:
> On Wed, 2013-04-03 at 13:59 +0800, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> > 
> > On Tue, Apr 02, 2013 at 02:00:55PM -0600, Stephen Warren wrote:
> > > On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > > > Adding the PM configuration of PMC when the platform support suspend
> > > > function.
> > > 
> > > For this patch, some more boards could be supported, but I think we'll
> > > have to rely on other people (Lucas, Thierry) to send patches for them,
> > > since they know the details of the board. It's fine to leave suspend
> > > disabled on those boards until later.
> > 
> > I'm not sure what would be the best way to get the Tamonten devices out
> > of suspend again. For Plutux and TEC we have a power button that could
> > possibly be reused. There's a WAKEUP pin on the Tamonten connector which
> > goes to GPIO PV2, but the mechanism to trigger it is carrier-board
> > dependent.
> > 
> > For the Medcom-Wide we don't have a power button, but it could possibly
> > use the WAKEUP pin if that's connected. It seems like in all designs it
> > goes to the CPLD, but I need to check with engineering if there's a way
> > to manipulate it.
> > 
> > So yes, I think for now we can leave suspend disabled on Tamonten and I
> > can send patches to enable it once I've clarified with engineering.
> > 
> Hi Thierry,
> 
> I just recall I still need at least "nvidia,cpu-pwr-good-time" and
> "nvidia,cpu-pwr-off-time" two properties to make CPU idle power-down
> mode (same with LP2) work normally after this series.
> 
> So can you provide me that or point me out where is your downstream
> kernel source? There data would be come from DT after this series.

We don't have suspend support in downstream kernels either. However
since the Tamonten was derived from the Harmony reference design I
suppose the same values can be reused.

That said, the binding document says that those values are only required
if nvidia,suspend-mode is set. So if we don't add it for the Tamonten
boards why would you need the cpu-pwr-good-time and cpu-pwr-off-time
values. Or maybe the binding document is wrong?

Thierry

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Re: [PATCH V5 9/9] ARM: dts: tegra: add the PM configurations of PMC

[Joseph Lo]

On Wed, 2013-04-03 at 15:04 +0800, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Wed, Apr 03, 2013 at 02:34:25PM +0800, Joseph Lo wrote:
> > On Wed, 2013-04-03 at 13:59 +0800, Thierry Reding wrote:
> > > > Old Signed by an unknown key
> > > 
> > > On Tue, Apr 02, 2013 at 02:00:55PM -0600, Stephen Warren wrote:
> > > > On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > > > > Adding the PM configuration of PMC when the platform support suspend
> > > > > function.
> > > > 
> > > > For this patch, some more boards could be supported, but I think we'll
> > > > have to rely on other people (Lucas, Thierry) to send patches for them,
> > > > since they know the details of the board. It's fine to leave suspend
> > > > disabled on those boards until later.
> > > 
> > > I'm not sure what would be the best way to get the Tamonten devices out
> > > of suspend again. For Plutux and TEC we have a power button that could
> > > possibly be reused. There's a WAKEUP pin on the Tamonten connector which
> > > goes to GPIO PV2, but the mechanism to trigger it is carrier-board
> > > dependent.
> > > 
> > > For the Medcom-Wide we don't have a power button, but it could possibly
> > > use the WAKEUP pin if that's connected. It seems like in all designs it
> > > goes to the CPLD, but I need to check with engineering if there's a way
> > > to manipulate it.
> > > 
> > > So yes, I think for now we can leave suspend disabled on Tamonten and I
> > > can send patches to enable it once I've clarified with engineering.
> > > 
> > Hi Thierry,
> > 
> > I just recall I still need at least "nvidia,cpu-pwr-good-time" and
> > "nvidia,cpu-pwr-off-time" two properties to make CPU idle power-down
> > mode (same with LP2) work normally after this series.
> > 
> > So can you provide me that or point me out where is your downstream
> > kernel source? There data would be come from DT after this series.
> 
> We don't have suspend support in downstream kernels either. However
> since the Tamonten was derived from the Harmony reference design I
> suppose the same values can be reused.
> 
OK. That's enough.

> That said, the binding document says that those values are only required
> if nvidia,suspend-mode is set. So if we don't add it for the Tamonten
> boards why would you need the cpu-pwr-good-time and cpu-pwr-off-time
> values. Or maybe the binding document is wrong?

Actually, when you support CPU idle power-down mode (LP2), you already
support suspend function (at least LP2 mode). Just no wake up source
define in DT for your boards.

May I add these properties to your boards (same as Harmony)? Then you
can figure out your wake up source later, at least the RTC can wake up
your device I believe.

Thanks,
Joseph

Re: [PATCH V5 9/9] ARM: dts: tegra: add the PM configurations of PMC

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 3196 bytes --]

On Wed, Apr 03, 2013 at 03:11:17PM +0800, Joseph Lo wrote:
> On Wed, 2013-04-03 at 15:04 +0800, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> > 
> > On Wed, Apr 03, 2013 at 02:34:25PM +0800, Joseph Lo wrote:
> > > On Wed, 2013-04-03 at 13:59 +0800, Thierry Reding wrote:
> > > > > Old Signed by an unknown key
> > > > 
> > > > On Tue, Apr 02, 2013 at 02:00:55PM -0600, Stephen Warren wrote:
> > > > > On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > > > > > Adding the PM configuration of PMC when the platform support suspend
> > > > > > function.
> > > > > 
> > > > > For this patch, some more boards could be supported, but I think we'll
> > > > > have to rely on other people (Lucas, Thierry) to send patches for them,
> > > > > since they know the details of the board. It's fine to leave suspend
> > > > > disabled on those boards until later.
> > > > 
> > > > I'm not sure what would be the best way to get the Tamonten devices out
> > > > of suspend again. For Plutux and TEC we have a power button that could
> > > > possibly be reused. There's a WAKEUP pin on the Tamonten connector which
> > > > goes to GPIO PV2, but the mechanism to trigger it is carrier-board
> > > > dependent.
> > > > 
> > > > For the Medcom-Wide we don't have a power button, but it could possibly
> > > > use the WAKEUP pin if that's connected. It seems like in all designs it
> > > > goes to the CPLD, but I need to check with engineering if there's a way
> > > > to manipulate it.
> > > > 
> > > > So yes, I think for now we can leave suspend disabled on Tamonten and I
> > > > can send patches to enable it once I've clarified with engineering.
> > > > 
> > > Hi Thierry,
> > > 
> > > I just recall I still need at least "nvidia,cpu-pwr-good-time" and
> > > "nvidia,cpu-pwr-off-time" two properties to make CPU idle power-down
> > > mode (same with LP2) work normally after this series.
> > > 
> > > So can you provide me that or point me out where is your downstream
> > > kernel source? There data would be come from DT after this series.
> > 
> > We don't have suspend support in downstream kernels either. However
> > since the Tamonten was derived from the Harmony reference design I
> > suppose the same values can be reused.
> > 
> OK. That's enough.
> 
> > That said, the binding document says that those values are only required
> > if nvidia,suspend-mode is set. So if we don't add it for the Tamonten
> > boards why would you need the cpu-pwr-good-time and cpu-pwr-off-time
> > values. Or maybe the binding document is wrong?
> 
> Actually, when you support CPU idle power-down mode (LP2), you already
> support suspend function (at least LP2 mode). Just no wake up source
> define in DT for your boards.

Okay, but for CPU idle LP2 we don't need a wakeup source, right? I only
need the wakeup source if I explicitly suspend the device.

> May I add these properties to your boards (same as Harmony)? Then you
> can figure out your wake up source later, at least the RTC can wake up
> your device I believe.

From what I understand there should be no changes in behaviour after
this patch, so it should be fine.

Thierry

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Re: [PATCH V5 9/9] ARM: dts: tegra: add the PM configurations of PMC

[Joseph Lo]

On Wed, 2013-04-03 at 15:19 +0800, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Wed, Apr 03, 2013 at 03:11:17PM +0800, Joseph Lo wrote:
> > On Wed, 2013-04-03 at 15:04 +0800, Thierry Reding wrote:
> > > > Old Signed by an unknown key
> > > 
> > > On Wed, Apr 03, 2013 at 02:34:25PM +0800, Joseph Lo wrote:
> > > > On Wed, 2013-04-03 at 13:59 +0800, Thierry Reding wrote:
> > > > > > Old Signed by an unknown key
> > > > > 
> > > > > On Tue, Apr 02, 2013 at 02:00:55PM -0600, Stephen Warren wrote:
> > > > > > On 04/02/2013 05:20 AM, Joseph Lo wrote:
> > > > > > > Adding the PM configuration of PMC when the platform support suspend
> > > > > > > function.
> > > > > > 
> > > > > > For this patch, some more boards could be supported, but I think we'll
> > > > > > have to rely on other people (Lucas, Thierry) to send patches for them,
> > > > > > since they know the details of the board. It's fine to leave suspend
> > > > > > disabled on those boards until later.
> > > > > 
> > > > > I'm not sure what would be the best way to get the Tamonten devices out
> > > > > of suspend again. For Plutux and TEC we have a power button that could
> > > > > possibly be reused. There's a WAKEUP pin on the Tamonten connector which
> > > > > goes to GPIO PV2, but the mechanism to trigger it is carrier-board
> > > > > dependent.
> > > > > 
> > > > > For the Medcom-Wide we don't have a power button, but it could possibly
> > > > > use the WAKEUP pin if that's connected. It seems like in all designs it
> > > > > goes to the CPLD, but I need to check with engineering if there's a way
> > > > > to manipulate it.
> > > > > 
> > > > > So yes, I think for now we can leave suspend disabled on Tamonten and I
> > > > > can send patches to enable it once I've clarified with engineering.
> > > > > 
> > > > Hi Thierry,
> > > > 
> > > > I just recall I still need at least "nvidia,cpu-pwr-good-time" and
> > > > "nvidia,cpu-pwr-off-time" two properties to make CPU idle power-down
> > > > mode (same with LP2) work normally after this series.
> > > > 
> > > > So can you provide me that or point me out where is your downstream
> > > > kernel source? There data would be come from DT after this series.
> > > 
> > > We don't have suspend support in downstream kernels either. However
> > > since the Tamonten was derived from the Harmony reference design I
> > > suppose the same values can be reused.
> > > 
> > OK. That's enough.
> > 
> > > That said, the binding document says that those values are only required
> > > if nvidia,suspend-mode is set. So if we don't add it for the Tamonten
> > > boards why would you need the cpu-pwr-good-time and cpu-pwr-off-time
> > > values. Or maybe the binding document is wrong?
> > 
> > Actually, when you support CPU idle power-down mode (LP2), you already
> > support suspend function (at least LP2 mode). Just no wake up source
> > define in DT for your boards.
> 
> Okay, but for CPU idle LP2 we don't need a wakeup source, right? I only
> need the wakeup source if I explicitly suspend the device.
> 
Yes. The difference between CPU idle and suspend LP2 is wake up from any
interrupt or specific interrupt source (wake up source for suspend).

My approach is adding CPU idle LP2 support first and make it support
suspend later. Then reorganize them into PM related code and get the
configurations from DT.

> > May I add these properties to your boards (same as Harmony)? Then you
> > can figure out your wake up source later, at least the RTC can wake up
> > your device I believe.
> 
> From what I understand there should be no changes in behaviour after
> this patch, so it should be fine.
> 
OK, thanks.

Re: [PATCH V5 0/9] ARM: tegra: add platform suspend support

[Stephen Warren]

On 04/02/2013 05:20 AM, Joseph Lo wrote:
> This series introduces a basic functionality for Tegra to support the
> platform suspend and resume.
> 
> Note: This series only adds the support for Tegra20 and Tegra30. The
> Tegra114 will be supported later.
> 
> Verified on Seaboard and Cardhu.

I've also reproduced this on those two boards:-)

It's a pity that the only way to wake up Cardhu is using the RTC's
wakealarm though. Still, we can add extra keyboard/GPIO keys/... to the
various board DTs after this basic support series is checked in.