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* [PATCH v2] clk: tegra: Make gr2d and gr3d clocks children of pll_c
@ 2013-04-02 14:18 Thierry Reding
       [not found] ` <1364912324-5576-1-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
  0 siblings, 1 reply; 3+ messages in thread
From: Thierry Reding @ 2013-04-02 14:18 UTC (permalink / raw)
  To: Mike Turquette
  Cc: Stephen Warren, Terje Bergström, Peter De Schrijver,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA

By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.

gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.

Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
---
Changes in v2:
- make the same changes for Tegra30

 drivers/clk/tegra/clk-tegra20.c | 2 ++
 drivers/clk/tegra/clk-tegra30.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bf19400..b020beb 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1247,6 +1247,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{host1x, pll_c, 150000000, 0},
 	{disp1, pll_p, 600000000, 0},
 	{disp2, pll_p, 600000000, 0},
+	{gr2d, pll_c, 300000000, 0},
+	{gr3d, pll_c, 300000000, 0},
 	{clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
 };
 
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba6f51b..b8b241d 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1911,6 +1911,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{disp1, pll_p, 600000000, 0},
 	{disp2, pll_p, 600000000, 0},
 	{twd, clk_max, 0, 1},
+	{gr2d, pll_c, 300000000, 0},
+	{gr3d, pll_c, 300000000, 0},
 	{clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
 };
 
-- 
1.8.2

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] clk: tegra: Make gr2d and gr3d clocks children of pll_c
       [not found] ` <1364912324-5576-1-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
@ 2013-04-02 16:09   ` Stephen Warren
  2013-04-03  4:39   ` Terje Bergström
  1 sibling, 0 replies; 3+ messages in thread
From: Stephen Warren @ 2013-04-02 16:09 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Mike Turquette, Terje Bergström, Peter De Schrijver,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA

On 04/02/2013 08:18 AM, Thierry Reding wrote:
> By default these clocks are children of pll_m, but in downstream kernels
> they are reparented to pll_c. While at it, decrease their frequencies to
> 300 MHz because the defaults aren't in the specified range.
> 
> gr2d can reportedly run at much higher frequencies, but 300 MHz works
> and is a more conservative default.

Applied to Tegra's for-3.10/clk branch. I assumed that Peter's and
Mike's acks carried over to V2.

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] clk: tegra: Make gr2d and gr3d clocks children of pll_c
       [not found] ` <1364912324-5576-1-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
  2013-04-02 16:09   ` Stephen Warren
@ 2013-04-03  4:39   ` Terje Bergström
  1 sibling, 0 replies; 3+ messages in thread
From: Terje Bergström @ 2013-04-03  4:39 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Mike Turquette, Stephen Warren, Peter De Schrijver,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

On 02.04.2013 17:18, Thierry Reding wrote:
> By default these clocks are children of pll_m, but in downstream kernels
> they are reparented to pll_c. While at it, decrease their frequencies to
> 300 MHz because the defaults aren't in the specified range.
> 
> gr2d can reportedly run at much higher frequencies, but 300 MHz works
> and is a more conservative default.
> 
> Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
> ---
> Changes in v2:
> - make the same changes for Tegra30
> 
>  drivers/clk/tegra/clk-tegra20.c | 2 ++
>  drivers/clk/tegra/clk-tegra30.c | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index bf19400..b020beb 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -1247,6 +1247,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
>  	{host1x, pll_c, 150000000, 0},
>  	{disp1, pll_p, 600000000, 0},
>  	{disp2, pll_p, 600000000, 0},
> +	{gr2d, pll_c, 300000000, 0},
> +	{gr3d, pll_c, 300000000, 0},
>  	{clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
>  };
>  
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index ba6f51b..b8b241d 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1911,6 +1911,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
>  	{disp1, pll_p, 600000000, 0},
>  	{disp2, pll_p, 600000000, 0},
>  	{twd, clk_max, 0, 1},
> +	{gr2d, pll_c, 300000000, 0},
> +	{gr3d, pll_c, 300000000, 0},
>  	{clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
>  };
>  
> 

Thanks, looks good.

Acked-By: Terje Bergstrom <tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Terje

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2013-04-03  4:39 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2013-04-02 14:18 [PATCH v2] clk: tegra: Make gr2d and gr3d clocks children of pll_c Thierry Reding
     [not found] ` <1364912324-5576-1-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
2013-04-02 16:09   ` Stephen Warren
2013-04-03  4:39   ` Terje Bergström

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