From: Stephen Warren <swarren@wwwdotorg.org>
To: Jay Agarwal <jagarwal@nvidia.com>
Cc: linux@arm.linux.org.uk, thierry.reding@avionic-design.de,
ldewangan@nvidia.com, bhelgaas@google.com, olof@lixom.net,
hdoyu@nvidia.com, pgaikwad@nvidia.com, mturquette@linaro.org,
pdeschrijver@nvidia.com, linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, jtukkinen@nvidia.com,
kthota@nvidia.com
Subject: Re: [PATCH 3/4] ARM: dts: tegra: Correct PCIe entry
Date: Wed, 08 May 2013 10:56:34 -0600 [thread overview]
Message-ID: <518A83C2.3070709@wwwdotorg.org> (raw)
In-Reply-To: <1368010660-31465-3-git-send-email-jagarwal@nvidia.com>
On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> - Add interrupt-names property
> - Correct downstream I/O size
> - Correct cml clock name for Tegra30
> - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> - and should be applied on top of this.
Another change that needs to be made to this file (probably as a
separate change that Thierry can squash into one of his earlier changes)
is to move the pcie-controller node; it is currently not in the correct
place in the .dtsi file; it's not sorted by reg addresss.
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
> <&tegra_car 118>, <&tegra_car 215>;
> - clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
> + clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml0";
You could drop that change if the driver named the clock "cml" rather
than "cml0", which as I explained in my previous email seems like a good
idea anyway.
Applying the same reasoning, I wonder if for Tegra 20 too, the PCIe
driver shouldn't expect clock names of just "xclk" and "pll" rather than
"pcie_xclk" and "pll_e".
next prev parent reply other threads:[~2013-05-08 16:56 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-08 10:57 [PATCH 1/4] ARM: tegra30: clocks: Fix pciex clock registration Jay Agarwal
2013-05-08 10:57 ` [PATCH 2/4] ARM: tegra: pcie: Add tegra3 support Jay Agarwal
[not found] ` <1368010660-31465-2-git-send-email-jagarwal-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-05-08 16:53 ` Stephen Warren
2013-05-08 10:57 ` [PATCH 3/4] ARM: dts: tegra: Correct PCIe entry Jay Agarwal
2013-05-08 16:56 ` Stephen Warren [this message]
[not found] ` <1368010660-31465-1-git-send-email-jagarwal-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-05-08 10:57 ` [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu Jay Agarwal
[not found] ` <1368010660-31465-4-git-send-email-jagarwal-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-05-08 17:04 ` Stephen Warren
[not found] ` <518A8596.7070702-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-05-08 17:53 ` Stephen Warren
2013-05-15 17:28 ` Jay Agarwal
2013-05-17 16:51 ` Jay Agarwal
2013-05-17 19:48 ` Stephen Warren
2013-05-29 10:10 ` Jay Agarwal
2013-05-29 15:35 ` Stephen Warren
2013-05-30 17:37 ` Jay Agarwal
[not found] ` <C79B248886DD134989C8FF6B096A91AB91B616BEA6-kdsAE/FnitNDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
2013-05-30 18:04 ` Stephen Warren
[not found] ` <C79B248886DD134989C8FF6B096A91AB91B616BEAD@BGMAIL01.nvidia.com>
[not found] ` <51A8DE3A.6080503@wwwdotorg.org>
[not found] ` <C79B248886DD134989C8FF6B096A91AB91B616BEB3@BGMAIL01.nvidia.com>
[not found] ` <C79B248886DD134989C8FF6B096A91AB91B616BEB4@BGMAIL01.nvidia.com>
[not found] ` <C79B248886DD134989C8FF6B096A91AB91B616BEB5@BGMAIL01.nvidia.com>
[not found] ` <C79B248886DD134989C8FF6B096A91AB91B616BEBE@BGMAIL01.nvidia.com>
[not found] ` <C79B248886DD134989C8FF6B096A91AB91B616BEC1@BGMAIL01.nvidia.com>
[not found] ` <C79B248886DD134989C8FF6B096A91AB91B616BEC1-kdsAE/FnitNDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
2013-06-04 17:17 ` FW: " Jay Agarwal
2013-05-08 16:36 ` [PATCH 1/4] ARM: tegra30: clocks: Fix pciex clock registration Stephen Warren
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