From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH] ARM: tegra: emc: correction of ram-code parsing from
 dt
Date: Mon, 20 May 2013 14:06:09 +0400
Message-ID: <5199F591.80409@gmail.com>
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18.05.2013 03:53, Stephen Warren =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
> On 05/12/2013 02:26 PM, Dmitry Osipenko wrote:
>> Change tegra_emc_ramcode_devnode() to get ram-code from child node i=
nstead of
>> parent.
>=20
> I've applied this to Tegra's for-3.11/soc branch.
>=20

Thanks.

>> For me it looks like it should be better to place ram-code inside of=
 table
>> nodes, so num_tables will be incremented if table has valid ram-code=
 and table
>> with invalid ram-code will be skipped on getting table params loop. =
This avoids
>> placing of #address-cells and #size-cells in nodes with ram-code.
>> If it looks ok, I may send new patch.
>=20
> That would be a change to the DT binding. DT bindings are supposed to=
 be
> a stable ABI, so we wouldn't want to change the binding unless there =
was
> a strong reason. I don't think there is one here.
>=20

Ok.