From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Jay Agarwal <jagarwal-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
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Subject: Re: [PATCH V1] ARM: dts: tegra: Modify pcie memory space size
Date: Thu, 20 Jun 2013 10:24:39 -0600 [thread overview]
Message-ID: <51C32CC7.5010109@wwwdotorg.org> (raw)
In-Reply-To: <1371712491-31070-1-git-send-email-jagarwal-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 06/20/2013 01:14 AM, Jay Agarwal wrote:
> - decrease non-prefetch memory size to 128 MB
> - increase prefetch memory size to 384 MB
> - above change is done because most pcie devices
> prefetch memory size requirement is quite higher
> compared to non-prefetch memory space.
It's possible this change won't be suitable for all applications. People
may simply need to adjust their DT based on what they want to connect.
Still, this patch probably biases things in the correct way for now.
Longer term, we might want to investigate dynamically sizing the windows
in order to support arbitrary attached devices, in much the same way as
the Marvell code does/will in order to conserve physical/bus address
space for their multiple controllers.
However, this change allows me to correctly enumerate a particular GPU I
have plugged into my Harmony board, and assign all the BARs, so:
Tested-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
next prev parent reply other threads:[~2013-06-20 16:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-20 7:14 [PATCH V1] ARM: dts: tegra: Modify pcie memory space size Jay Agarwal
[not found] ` <1371712491-31070-1-git-send-email-jagarwal-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-06-20 16:24 ` Stephen Warren [this message]
2013-06-21 5:30 ` Jay Agarwal
[not found] ` <C79B248886DD134989C8FF6B096A91AB91CF1615EC-kdsAE/FnitNDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
2013-06-21 6:16 ` Stephen Warren
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