From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH] clk: tegra114: Initialize host1x and related clocks Date: Tue, 24 Sep 2013 11:20:18 -0600 Message-ID: <5241C9D2.9050002@wwwdotorg.org> References: <1380015604-21956-1-git-send-email-treding@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1380015604-21956-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding Cc: Mike Turquette , Peter De Schrijver , Prashant Gaikwad , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Mikko Perttunen List-Id: linux-tegra@vger.kernel.org On 09/24/2013 03:40 AM, Thierry Reding wrote: > From: Mikko Perttunen > > The host1x clock should be a child of PLLC and runs too fast by default, > so throttle it while at it. The disp1 and disp2 clocks should use PLLP > by default. They will usually be reparented to either pll_d_out0 or > pll_d2_out0 as part of the display driver setup. Acked-by: Stephen Warren