From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH] HACK: clk: tegra: Do not mark PLLE as fixed
Date: Tue, 29 Oct 2013 13:41:58 -0600 [thread overview]
Message-ID: <52700F86.2080103@wwwdotorg.org> (raw)
In-Reply-To: <1383057631-32668-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 10/29/2013 08:40 AM, Thierry Reding wrote:
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
What does this patch solve? A description would be nice.
I thought that this PLL essentially was fixed; while it may have some
registers than /can/ change the rate, hasn't the HW team only
characterized it to run at the single frequency that PCIe requires,
hence SW is supposed to treat it as fixed?
next prev parent reply other threads:[~2013-10-29 19:41 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-29 14:40 [PATCH] HACK: clk: tegra: Do not mark PLLE as fixed Thierry Reding
[not found] ` <1383057631-32668-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-29 19:41 ` Stephen Warren [this message]
[not found] ` <52700F86.2080103-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-10-30 20:44 ` Thierry Reding
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