From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Subject: Re: [PATCH] HACK: clk: tegra: Do not mark PLLE as fixed
Date: Tue, 29 Oct 2013 13:41:58 -0600
Message-ID: <52700F86.2080103@wwwdotorg.org>
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To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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On 10/29/2013 08:40 AM, Thierry Reding wrote:
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

What does this patch solve? A description would be nice.

I thought that this PLL essentially was fixed; while it may have some
registers than /can/ change the rate, hasn't the HW team only
characterized it to run at the single frequency that PCIe requires,
hence SW is supposed to treat it as fixed?