Re: [PATCH 3/3] clk: tegra: Properly setup PWM clock on Tegra30

[Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]

On 10/29/2013 09:51 AM, Thierry Reding wrote:
> The clock for the PWM controller is slightly different from other
> peripheral clocks on Tegra30. The clock source mux field start at
> bit position 28 rather than 30.

I think you need to CC this series to Mike Turquette and relevant lists
for review. While Peter is sending pull requests to Mike for the Tegra
clock driver, Mike still needs to see the patches before that happens.

> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c

> @@ -836,7 +837,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
>  	[tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
>  	[tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
>  	[tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
> -	[tegra_clk_pwm] = { .dt_id = TEGRA30_CLK_PWM, .present = true },

I think you still need an entry in this table; isn't it used by the
DT->internal clock ID translation function?

Either way, it seems like this patch might want to add a
tegra_clk_pwm_tegra30 so that the common C files can still implement
this clock, just with different parameters?