From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH 1/2] ARM: tegra: Correct Tegra30 SMMU register map Date: Tue, 12 Nov 2013 12:19:04 -0700 Message-ID: <52827F28.7020305@wwwdotorg.org> References: <1383796706-10729-1-git-send-email-markz@nvidia.com> <1383796706-10729-2-git-send-email-markz@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1383796706-10729-2-git-send-email-markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Mark Zhang , hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 11/06/2013 08:58 PM, Mark Zhang wrote: > Correct Tegra30 SMMU register map. Some more explanation is required here re: why this layout is more correct than what's there. Do you need to edit the reg property in Tegra30's memory-controller node too; that's what all these reg ranges are interleaved with, so presumably if there was a mistake in the SMMU ranges, there's the equivalent inverse mistake in the MC's ranges? The DT binding for nvidia,tegra30-smmu states that reg should include precisely 3 entries. This patch no longer conforms to that. The binding needs to be re-written to explain the interleaving issue, and say that an arbitrary number of ranges may be provided. The same issue exists in the nvidia,tegra30-mc DT binding. I think I'm beginning to regret separating out the MC and SMMU into separate DT nodes:-(