Re: [PATCH 1/2] ARM: tegra: Correct Tegra30 SMMU register map

[Mark Zhang <markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]

Hiroshi has mentioned that the TRM should be revised. :)
Because there are some registers which are needed by SMMU driver while
they're not in TRM yet.

So this patch doesn't make sense now. Thanks for the review.

Mark
On 11/13/2013 03:19 AM, Stephen Warren wrote:
> On 11/06/2013 08:58 PM, Mark Zhang wrote:
>> Correct Tegra30 SMMU register map.
> 
> Some more explanation is required here re: why this layout is more
> correct than what's there.
> 
> Do you need to edit the reg property in Tegra30's memory-controller node
> too; that's what all these reg ranges are interleaved with, so
> presumably if there was a mistake in the SMMU ranges, there's the
> equivalent inverse mistake in the MC's ranges?
> 
> The DT binding for nvidia,tegra30-smmu states that reg should include
> precisely 3 entries. This patch no longer conforms to that. The binding
> needs to be re-written to explain the interleaving issue, and say that
> an arbitrary number of ranges may be provided. The same issue exists in
> the nvidia,tegra30-mc DT binding.
> 
> I think I'm beginning to regret separating out the MC and SMMU into
> separate DT nodes:-(
>