From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Matthew Longnecker
<mlongnecker-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH 5/6] ARM: DTS: tegra: add DFLL integration to the Dalmore DTS file
Date: Thu, 19 Dec 2013 17:10:17 -0700 [thread overview]
Message-ID: <52B38AE9.2030209@wwwdotorg.org> (raw)
In-Reply-To: <20131219124929.3226.79335.stgit@tamien>
On 12/19/2013 05:49 AM, Paul Walmsley wrote:
> Expose the DFLL device on the NVIDIA Tegra114 Dalmore board, and connect
> the DFLL (and FCPU cluster) voltage regulator.
> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt
> +NVIDIA Tegra114 DFLL clocksource data in the board DTS file
> +
> +Optional properties:
> +
> +- status : device availability -- managed by the DT integration code, not
> + the DFLL driver. Should be set to "okay" if the DFLL is to be
> + used on this board type.
There's certainly no need to document the same DT property twice. The DT
docs are about documenting the schema. If the DT author decides to split
the properties between a .dtsi and a .dts file, that's irrelevant to the
schema.
next prev parent reply other threads:[~2013-12-20 0:10 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-19 12:36 [PATCH 0/6] clk: tegra: add basic support for the DFLL clocksource Paul Walmsley
2013-12-19 12:36 ` [PATCH 1/6] ARM: tegra: fuse: add functions to read speedo ID and process ID Paul Walmsley
2013-12-19 23:09 ` Stephen Warren
2013-12-19 12:36 ` [PATCH 2/6] ARM: tegra114: fuse: add DFLL FCPU minimum voltage override test function Paul Walmsley
2013-12-19 23:12 ` Stephen Warren
2013-12-19 12:37 ` [PATCH 3/6] clk: tegra: add library for the DFLL clocksource (open-loop mode) Paul Walmsley
2013-12-19 23:57 ` Stephen Warren
2013-12-19 12:49 ` [PATCH 4/6] ARM: DTS: tegra: add the DFLL IP block to the T114 SoC file Paul Walmsley
2013-12-20 0:05 ` Stephen Warren
[not found] ` <52B389CD.8010004-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-01-14 6:27 ` Paul Walmsley
2014-01-14 6:32 ` Paul Walmsley
2014-01-15 19:50 ` Gerhard Sittig
[not found] ` <20140115195025.GU20094-kDjWylLy9wD0K7fsECOQyeGNnDKD8DIp@public.gmane.org>
2014-01-15 20:09 ` Paul Walmsley
[not found] ` <52D4D314.3000208@nvidia.com>
[not found] ` <52D4D314.3000208-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-01-14 17:43 ` Stephen Warren
2013-12-19 12:49 ` [PATCH 5/6] ARM: DTS: tegra: add DFLL integration to the Dalmore DTS file Paul Walmsley
2013-12-20 0:10 ` Stephen Warren [this message]
[not found] ` <52B38AE9.2030209-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-01-14 6:36 ` Paul Walmsley
2013-12-19 12:49 ` [PATCH 6/6] clk: tegra: add Tegra114 FCPU DFLL clocksource platform driver Paul Walmsley
2013-12-20 0:18 ` Stephen Warren
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