* [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree
@ 2014-08-13 1:56 Dylan Reid
[not found] ` <1407894967-18300-1-git-send-email-dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
0 siblings, 1 reply; 28+ messages in thread
From: Dylan Reid @ 2014-08-13 1:56 UTC (permalink / raw)
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA
Cc: swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
abrestic-F7+t8E8rja9g9hUCZPvPmw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
olof-nZhT3qVonbNeoWH0uzbU5w, Dylan Reid
The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124
processor and is similar to the Venice2 reference platform.
The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested
and work on the 1366x768 models. I haven't tried on the HD systems
yet.
WiFi does not yet work, it needs at least some PMIC changes to enable
the 32k clock.
The elan trackpad is not yet functional but hopefully will be soon as
there are patches under review.
There is also an issue on reboot because the TPM isn't reset. It will
cause the stock firmware to enter recovery mode. This can be worked
around by an EC-reset, press refresh and power at the same time.
Signed-off-by: Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra124-big.dts | 1137 ++++++++++++++++++++++++++++++++++++
2 files changed, 1138 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra124-big.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index acb6b42..b0ab6a6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -439,6 +439,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra114-roth.dtb \
tegra114-tn7.dtb \
+ tegra124-big.dtb \
tegra124-jetson-tk1.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts
new file mode 100644
index 0000000..aa0cd9f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-big.dts
@@ -0,0 +1,1137 @@
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+
+/ {
+ model = "Google Big";
+ compatible = "google,nyan-big", "nvidia,tegra124";
+
+ aliases {
+ rtc0 = "/i2c@0,7000d000/pmic@40";
+ rtc1 = "/rtc@0,7000e000";
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ host1x@0,50000000 {
+ hdmi@0,54280000 {
+ status = "okay";
+
+ vdd-supply = <&vdd_3v3_hdmi>;
+ pll-supply = <&vdd_hdmi_pll>;
+ hdmi-supply = <&vdd_5v0_hdmi>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio =
+ <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+ };
+
+ sor@0,54540000 {
+ status = "okay";
+
+ nvidia,dpaux = <&dpaux>;
+ nvidia,panel = <&panel>;
+ };
+
+ dpaux: dpaux@0,545c0000 {
+ vdd-supply = <&vdd_3v3_panel>;
+ status = "okay";
+ };
+ };
+
+ pinmux: pinmux@0,70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_default>;
+
+ pinmux_default: common {
+ dap_mclk1_pw4 {
+ nvidia,pins = "dap_mclk1_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ dap2_din_pa4 {
+ nvidia,pins = "dap2_din_pa4";
+ nvidia,function = "i2s1";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ dap2_dout_pa5 {
+ nvidia,pins = "dap2_dout_pa5",
+ "dap2_fs_pa2",
+ "dap2_sclk_pa3";
+ nvidia,function = "i2s1";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ dvfs_pwm_px0 {
+ nvidia,pins = "dvfs_pwm_px0",
+ "dvfs_clk_px2";
+ nvidia,function = "cldvfs";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_nxt_py2",
+ "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_dir_py1 {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "spi1";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pg4 {
+ nvidia,pins = "pg4",
+ "pg5",
+ "pg6",
+ "pi3";
+ nvidia,function = "spi4";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ pg7 {
+ nvidia,pins = "pg7";
+ nvidia,function = "spi4";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ ph1 {
+ nvidia,pins = "ph1";
+ nvidia,function = "pwm1";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ pk0 {
+ nvidia,pins = "pk0",
+ "kb_row15_ps7",
+ "clk_32k_out_pa0";
+ nvidia,function = "soc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "kb_col4_pq4",
+ "sdmmc3_clk_lb_out_pee4",
+ "sdmmc3_clk_lb_in_pee5",
+ "sdmmc3_cd_n_pv2";
+ nvidia,function = "sdmmc3";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc4_cmd_pt7 {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck";
+ nvidia,function = "rtck";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ clk_32k_in {
+ nvidia,pins = "clk_32k_in";
+ nvidia,function = "clk";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ core_pwr_req {
+ nvidia,pins = "core_pwr_req";
+ nvidia,function = "pwron";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ cpu_pwr_req {
+ nvidia,pins = "cpu_pwr_req";
+ nvidia,function = "cpu";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ pwr_int_n {
+ nvidia,pins = "pwr_int_n";
+ nvidia,function = "pmi";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ reset_out_n {
+ nvidia,pins = "reset_out_n";
+ nvidia,function = "reset_out_n";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ gen1_i2c_sda_pc5 {
+ nvidia,pins = "gen1_i2c_sda_pc5",
+ "gen1_i2c_scl_pc4";
+ nvidia,function = "i2c1";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "rsvd1";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row10_ps2 {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row9_ps1 {
+ nvidia,pins = "kb_row9_ps1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ usb_vbus_en0_pn4 {
+ nvidia,pins = "usb_vbus_en0_pn4",
+ "usb_vbus_en1_pn5";
+ nvidia,function = "usb";
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <36>;
+ nvidia,pull-up-strength = <20>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
+ };
+ drive_sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <22>;
+ nvidia,pull-up-strength = <36>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive_gma {
+ nvidia,pins = "drive_gma";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <2>;
+ nvidia,pull-up-strength = <1>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,drive-type = <1>;
+ };
+ codec_irq_l {
+ nvidia,pins = "ph4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_bl_en {
+ nvidia,pins = "ph2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch_irq_l {
+ nvidia,pins = "gpio_w3_aud_pw3";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ tpm_davint_l {
+ nvidia,pins = "ph6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ts_irq_l {
+ nvidia,pins = "pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ts_reset_l {
+ nvidia,pins = "pk4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ts_shdn_l {
+ nvidia,pins = "pk1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph7 {
+ nvidia,pins = "ph7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col0_ap {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lid_open {
+ nvidia,pins = "kb_row4_pr4";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ en_vdd_sd {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ac_ok {
+ nvidia,pins = "pj0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sensor_irq_l {
+ nvidia,pins = "pi6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ wifi_en {
+ nvidia,pins = "gpio_x7_aud_px7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ en_vdd_bl {
+ nvidia,pins = "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ en_vdd_hdmi {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ soc_warm_reset_l {
+ nvidia,pins = "pi5";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hp_det_l {
+ nvidia,pins = "pi7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mic_det_l {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ serial@0,70006000 {
+ status = "okay";
+ };
+
+ pwm: pwm@0,7000a000 {
+ status = "okay";
+ };
+
+ i2c@0,7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ acodec: audio-codec@10 {
+ compatible = "maxim,max98090";
+ reg = <0x10>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ i2c@0,7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@0,7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tpm@20 {
+ compatible = "infineon,slb9645tt";
+ reg = <0x20>;
+ };
+ };
+
+ hdmi_ddc: i2c@0,7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@0,7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: pmic@40 {
+ compatible = "ams,as3722";
+ reg = <0x40>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ ams,system-power-controller;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&as3722_default>;
+
+ as3722_default: pinmux {
+ gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ gpio1 {
+ pins = "gpio1";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ gpio2_4_7 {
+ pins = "gpio2", "gpio4", "gpio7";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ gpio3_6 {
+ pins = "gpio3", "gpio6";
+ bias-high-impedance;
+ };
+
+ gpio5 {
+ pins = "gpio5";
+ function = "clk32k-out";
+ bias-pull-down;
+ };
+ };
+
+ regulators {
+ vsup-sd2-supply = <&vdd_5v0_sys>;
+ vsup-sd3-supply = <&vdd_5v0_sys>;
+ vsup-sd4-supply = <&vdd_5v0_sys>;
+ vsup-sd5-supply = <&vdd_5v0_sys>;
+ vin-ldo0-supply = <&vdd_1v35_lp0>;
+ vin-ldo1-6-supply = <&vdd_3v3_run>;
+ vin-ldo2-5-7-supply = <&vddio_1v8>;
+ vin-ldo3-4-supply = <&vdd_3v3_sys>;
+ vin-ldo9-10-supply = <&vdd_5v0_sys>;
+ vin-ldo11-supply = <&vdd_3v3_run>;
+
+ sd0 {
+ regulator-name = "+VDD_CPU_AP";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ams,ext-control = <2>;
+ };
+
+ sd1 {
+ regulator-name = "+VDD_CORE";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microamp = <2500000>;
+ regulator-max-microamp = <4000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ams,ext-control = <1>;
+ };
+
+ vdd_1v35_lp0: sd2 {
+ regulator-name = "+1.35V_LP0(sd2)";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sd3 {
+ regulator-name = "+1.35V_LP0(sd3)";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v05_run: sd4 {
+ regulator-name = "+1.05V_RUN";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vddio_1v8: sd5 {
+ regulator-name = "+1.8V_VDDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sd6 {
+ regulator-name = "+VDD_GPU_AP";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo0 {
+ regulator-name = "+1.05V_RUN_AVDD";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ams,ext-control = <1>;
+ };
+
+ ldo1 {
+ regulator-name = "+1.8V_RUN_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo2 {
+ regulator-name = "+1.2V_GEN_AVDD";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3 {
+ regulator-name = "+1.00V_LP0_VDD_RTC";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ams,enable-tracking;
+ };
+
+ vdd_run_cam: ldo4 {
+ regulator-name = "+3.3V_RUN_CAM";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo5 {
+ regulator-name = "+1.2V_RUN_CAM_FRONT";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vddio_sdmmc3: ldo6 {
+ regulator-name = "+VDDIO_SDMMC3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo7 {
+ regulator-name = "+1.05V_RUN_CAM_REAR";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ ldo9 {
+ regulator-name = "+2.8V_RUN_TOUCH";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo10 {
+ regulator-name = "+2.8V_RUN_CAM_AF";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo11 {
+ regulator-name = "+1.8V_RUN_VPP_FUSE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+ };
+
+ spi@0,7000d400 {
+ status = "okay";
+
+ cros_ec: cros-ec@0 {
+ compatible = "google,cros-ec-spi";
+ spi-max-frequency = <3000000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+ reg = <0>;
+
+ google,cros-ec-spi-msg-delay = <2000>;
+
+ i2c-tunnel {
+ compatible = "google,cros-ec-i2c-tunnel";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ google,remote-bus = <0>;
+
+ charger: bq24735@9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(J, 0)
+ GPIO_ACTIVE_HIGH>;
+ ti,ac-detect-gpios = <&gpio
+ TEGRA_GPIO(J, 0)
+ GPIO_ACTIVE_HIGH>;
+ };
+
+ battery: sbs-battery@b {
+ compatible = "sbs,sbs-battery";
+ reg = <0xb>;
+ sbs,i2c-retry-count = <2>;
+ sbs,poll-retry-count = <10>;
+ power-supplies = <&charger>;
+ };
+ };
+ };
+ };
+
+ spi@0,7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ spi-flash@0 {
+ compatible = "winbond,w25q32dw";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+ };
+
+ pmc@0,7000e400 {
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <0>;
+ nvidia,cpu-pwr-good-time = <500>;
+ nvidia,cpu-pwr-off-time = <300>;
+ nvidia,core-pwr-good-time = <641 3845>;
+ nvidia,core-pwr-off-time = <61036>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+ };
+
+ hda@0,70030000 {
+ status = "okay";
+ };
+
+ sdhci@0,700b0000 {
+ status = "okay";
+ power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ };
+
+ sdhci@0,700b0400 {
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ no-1-8-v;
+ vqmmc-supply = <&vddio_sdmmc3>;
+ };
+
+ sdhci@0,700b0600 {
+ status = "okay";
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ };
+
+ ahub@0,70300000 {
+ i2s@0,70301100 {
+ status = "okay";
+ };
+ };
+
+ usb@0,7d000000 {
+ status = "okay";
+ };
+
+ usb-phy@0,7d000000 {
+ status = "okay";
+ vbus-supply = <&vdd_usb1_vbus>;
+ };
+
+ usb@0,7d004000 {
+ status = "okay";
+ };
+
+ usb-phy@0,7d004000 {
+ status = "okay";
+ vbus-supply = <&vdd_run_cam>;
+ };
+
+ usb@0,7d008000 {
+ status = "okay";
+ };
+
+ usb-phy@0,7d008000 {
+ status = "okay";
+ vbus-supply = <&vdd_usb3_vbus>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_led>;
+ pwms = <&pwm 1 1000000>;
+
+ default-brightness-level = <224>;
+ brightness-levels =
+ < 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23
+ 24 25 26 27 28 29 30 31
+ 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255
+ 256>;
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ lid {
+ label = "Lid";
+ gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+ linux,input-type = <5>;
+ linux,code = <0>;
+ debounce-interval = <1>;
+ gpio-key,wakeup;
+ };
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <30>;
+ gpio-key,wakeup;
+ };
+ };
+
+ panel: panel {
+ compatible = "auo,b133xtn01", "simple-panel";
+
+ backlight = <&backlight>;
+ ddc-i2c-bus = <&dpaux>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_mux: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "+VDD_MUX";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_5v0_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "+5V_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
+
+ vdd_3v3_sys: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "+3.3V_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
+
+ vdd_3v3_run: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "+3.3V_RUN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_3v3_hdmi: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_3v3_run>;
+ };
+
+ vdd_led: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "+VDD_LED";
+ gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_mux>;
+ };
+
+ vdd_5v0_ts: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "+5V_VDD_TS_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_usb1_vbus: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ regulator-name = "+5V_USB_HS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_usb3_vbus: regulator@8 {
+ compatible = "regulator-fixed";
+ reg = <8>;
+ regulator-name = "+5V_USB_SS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_3v3_panel: regulator@9 {
+ compatible = "regulator-fixed";
+ reg = <9>;
+ regulator-name = "+3.3V_PANEL";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_run>;
+ };
+
+ vdd_3v3_lp0: regulator@10 {
+ compatible = "regulator-fixed";
+ reg = <10>;
+ regulator-name = "+3.3V_LP0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ /*
+ * TODO: find a way to wire this up with the USB EHCI
+ * controllers so that it can be enabled on demand.
+ */
+ regulator-always-on;
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_hdmi_pll: regulator@11 {
+ compatible = "regulator-fixed";
+ reg = <11>;
+ regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+ vin-supply = <&vdd_1v05_run>;
+ };
+
+ vdd_5v0_hdmi: regulator@12 {
+ compatible = "regulator-fixed";
+ reg = <12>;
+ regulator-name = "+5V_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-max98090-venice2",
+ "nvidia,tegra-audio-max98090";
+ nvidia,model = "NVIDIA Tegra Venice2";
+
+ nvidia,audio-routing =
+ "Headphones", "HPR",
+ "Headphones", "HPL",
+ "Speakers", "SPKR",
+ "Speakers", "SPKL",
+ "Mic Jack", "MICBIAS",
+ "DMICL", "Int Mic",
+ "DMICR", "Int Mic",
+ "IN34", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&acodec>;
+
+ clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+ <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
+ nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7)
+ GPIO_ACTIVE_HIGH>;
+ };
+};
+
+#include "cros-ec-keyboard.dtsi"
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply related [flat|nested] 28+ messages in thread[parent not found: <1407894967-18300-1-git-send-email-dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <1407894967-18300-1-git-send-email-dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> @ 2014-08-13 8:53 ` Thierry Reding 2014-08-13 16:23 ` Andrew Bresticker ` (3 more replies) 2014-08-13 17:10 ` Stephen Warren ` (2 subsequent siblings) 3 siblings, 4 replies; 28+ messages in thread From: Thierry Reding @ 2014-08-13 8:53 UTC (permalink / raw) To: Dylan Reid Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, swarren-3lzwWm7+Weoh9ZMKESR00Q, abrestic-F7+t8E8rja9g9hUCZPvPmw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, olof-nZhT3qVonbNeoWH0uzbU5w [-- Attachment #1: Type: text/plain, Size: 8551 bytes --] On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: > The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 > processor and is similar to the Venice2 reference platform. > > The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested > and work on the 1366x768 models. I haven't tried on the HD systems > yet. Presumably the HD systems will have a different compatible? Is it only the panel that's different or are there other changes? > There is also an issue on reboot because the TPM isn't reset. It will > cause the stock firmware to enter recovery mode. This can be worked > around by an EC-reset, press refresh and power at the same time. It's not clear to me what exactly this implies. Does it mean the system won't boot unless you manually press "refresh" and "power"? Are those keyboard buttons or keys on some debug board? > diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts > new file mode 100644 > index 0000000..aa0cd9f > --- /dev/null > +++ b/arch/arm/boot/dts/tegra124-big.dts > @@ -0,0 +1,1137 @@ > +/dts-v1/; > + > +#include <dt-bindings/input/input.h> > +#include "tegra124.dtsi" > + > +/ { > + model = "Google Big"; Perhaps this should at least mention that it's the Acer Chromebook 13. Otherwise this could just as well be some random development board. > + compatible = "google,nyan-big", "nvidia,tegra124"; What's "nyan"? Are there other variants of "big" other than "nyan"? > + pinmux: pinmux@0,70000868 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinmux_default>; > + > + pinmux_default: common { > + dap_mclk1_pw4 { > + nvidia,pins = "dap_mclk1_pw4"; > + nvidia,function = "extperiph1"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; Stephen proposed a patch not so long ago that removes the static pinmux settings from DTS files[0]. I'd expect he'll have objections to this DTS providing the static settings. The assumption with that patch is that the bootloader will have to set up the entire pinmux anyway (to prevent conflicting settings), therefore there'd be no need to do it in the kernel. Is this something that your bootloader already does (or could be modified to do)? [0]: http://patchwork.ozlabs.org/patch/363222/ > + serial@0,70006000 { > + status = "okay"; > + }; We've started to annotate some of these nodes in other DTS files to make it easier for people to match them to connectors on the board (or the schematics). This isn't necessarily important for things like PWM, since their use is fairly obvious and usually in-kernel only (with perhaps an exception of a PWM routed to some expansion header on some development board). For generic interfaces it's good to know what they map to on the device. Is this serial available as an accessible connector? Or is it some debug serial that's only available on a (non-equipped) header on the board? > + i2c@0,7000c400 { > + status = "okay"; > + clock-frequency = <100000>; > + }; > + > + i2c@0,7000c500 { > + status = "okay"; > + clock-frequency = <400000>; > + > + tpm@20 { > + compatible = "infineon,slb9645tt"; > + reg = <0x20>; > + }; I presume this is the TPM that you said isn't reset on reboot? Do you know the reason for why it isn't being reset? What's needed to reset this module? I assume it's something that can (and will eventually) be fixed? > + cros_ec: cros-ec@0 { > + compatible = "google,cros-ec-spi"; > + spi-max-frequency = <3000000>; > + interrupt-parent = <&gpio>; > + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; > + reg = <0>; > + > + google,cros-ec-spi-msg-delay = <2000>; > + > + i2c-tunnel { > + compatible = "google,cros-ec-i2c-tunnel"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + google,remote-bus = <0>; > + > + charger: bq24735@9 { > + compatible = "ti,bq24735"; > + reg = <0x9>; > + interrupt-parent = <&gpio>; > + interrupts = <TEGRA_GPIO(J, 0) > + GPIO_ACTIVE_HIGH>; > + ti,ac-detect-gpios = <&gpio > + TEGRA_GPIO(J, 0) > + GPIO_ACTIVE_HIGH>; Given this, I wonder how useful the 80-chars limit is for DTS files... > + battery: sbs-battery@b { > + compatible = "sbs,sbs-battery"; > + reg = <0xb>; > + sbs,i2c-retry-count = <2>; > + sbs,poll-retry-count = <10>; > + power-supplies = <&charger>; The sbs-battery binding doesn't define a power-supplies property. > + spi@0,7000da00 { > + status = "okay"; > + spi-max-frequency = <25000000>; > + spi-flash@0 { I think it's customary to separate the properties and child nodes using a blank line. Also, and I know other DTS files contain the same, I think spi-flash is kind of redundant, since it's a child of an SPI node. > + compatible = "winbond,w25q32dw"; > + reg = <0>; > + spi-max-frequency = <25000000>; Isn't the maximum frequency inherited from the parent? > + sdhci@0,700b0000 { > + status = "okay"; > + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; > + bus-width = <4>; > + no-1-8-v; > + non-removable; > + }; > + > + sdhci@0,700b0400 { > + status = "okay"; > + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; > + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; > + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; > + bus-width = <4>; > + no-1-8-v; > + vqmmc-supply = <&vddio_sdmmc3>; > + }; > + > + sdhci@0,700b0600 { > + status = "okay"; > + bus-width = <8>; > + no-1-8-v; > + non-removable; > + }; For these it might be good to know which is the external one (I assume there is one). I'm guessing sdhc@0,700b0000 is eMMC because it is marked non-removable, but a comment would be good to make it explicit. > + usb@0,7d000000 { > + status = "okay"; > + }; > + > + usb-phy@0,7d000000 { > + status = "okay"; > + vbus-supply = <&vdd_usb1_vbus>; > + }; > + > + usb@0,7d004000 { > + status = "okay"; > + }; > + > + usb-phy@0,7d004000 { > + status = "okay"; > + vbus-supply = <&vdd_run_cam>; > + }; > + > + usb@0,7d008000 { > + status = "okay"; > + }; > + > + usb-phy@0,7d008000 { > + status = "okay"; > + vbus-supply = <&vdd_usb3_vbus>; > + }; Similarly for these. > + > + backlight: backlight { > + compatible = "pwm-backlight"; > + > + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; > + power-supply = <&vdd_led>; > + pwms = <&pwm 1 1000000>; > + > + default-brightness-level = <224>; > + brightness-levels = > + < 0 1 2 3 4 5 6 7 > + 8 9 10 11 12 13 14 15 > + 16 17 18 19 20 21 22 23 > + 24 25 26 27 28 29 30 31 > + 32 33 34 35 36 37 38 39 > + 40 41 42 43 44 45 46 47 > + 48 49 50 51 52 53 54 55 > + 56 57 58 59 60 61 62 63 > + 64 65 66 67 68 69 70 71 > + 72 73 74 75 76 77 78 79 > + 80 81 82 83 84 85 86 87 > + 88 89 90 91 92 93 94 95 > + 96 97 98 99 100 101 102 103 > + 104 105 106 107 108 109 110 111 > + 112 113 114 115 116 117 118 119 > + 120 121 122 123 124 125 126 127 > + 128 129 130 131 132 133 134 135 > + 136 137 138 139 140 141 142 143 > + 144 145 146 147 148 149 150 151 > + 152 153 154 155 156 157 158 159 > + 160 161 162 163 164 165 166 167 > + 168 169 170 171 172 173 174 175 > + 176 177 178 179 180 181 182 183 > + 184 185 186 187 188 189 190 191 > + 192 193 194 195 196 197 198 199 > + 200 201 202 203 204 205 206 207 > + 208 209 210 211 212 213 214 215 > + 216 217 218 219 220 221 222 223 > + 224 225 226 227 228 229 230 231 > + 232 233 234 235 236 237 238 239 > + 240 241 242 243 244 245 246 247 > + 248 249 250 251 252 253 254 255 > + 256>; I'm curious, does ChromeOS really need 257 levels of brightness? I don't think I've seen a consumer product that supports more than a dozen levels. > + panel: panel { > + compatible = "auo,b133xtn01", "simple-panel"; There was a discussion a few days ago about this, and "simple-panel" really isn't useful in the list of compatible strings. I already have a patch queued up that removes that entry from all existing device trees and also gets rid of the OF match table entry in the panel-simple driver. Thierry [-- Attachment #2: Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree 2014-08-13 8:53 ` Thierry Reding @ 2014-08-13 16:23 ` Andrew Bresticker 2014-08-13 16:51 ` Olof Johansson ` (2 subsequent siblings) 3 siblings, 0 replies; 28+ messages in thread From: Andrew Bresticker @ 2014-08-13 16:23 UTC (permalink / raw) To: Thierry Reding Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On Wed, Aug 13, 2014 at 1:53 AM, Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> processor and is similar to the Venice2 reference platform. >> >> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> and work on the 1366x768 models. I haven't tried on the HD systems >> yet. > > Presumably the HD systems will have a different compatible? They do not. ChromeOS kernels just parse the EDID, so I suppose we'll need something similar here to support the HD panel. > Is it only the panel that's different or are there other changes? Only the panel is different. >> There is also an issue on reboot because the TPM isn't reset. It will >> cause the stock firmware to enter recovery mode. This can be worked >> around by an EC-reset, press refresh and power at the same time. > > It's not clear to me what exactly this implies. Does it mean the system > won't boot unless you manually press "refresh" and "power"? Are those > keyboard buttons or keys on some debug board? The system will enter recovery mode (and thus won't boot) unless you do an EC reset. Refresh and power are keys on the keyboard. >> diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts >> new file mode 100644 >> index 0000000..aa0cd9f >> --- /dev/null >> +++ b/arch/arm/boot/dts/tegra124-big.dts >> @@ -0,0 +1,1137 @@ >> +/dts-v1/; >> + >> +#include <dt-bindings/input/input.h> >> +#include "tegra124.dtsi" >> + >> +/ { >> + model = "Google Big"; > > Perhaps this should at least mention that it's the Acer Chromebook 13. > Otherwise this could just as well be some random development board. The convention for other Chromebooks so far (see exynos5420-peach-pit.dts for example) has just been to include the Google board name. >> + compatible = "google,nyan-big", "nvidia,tegra124"; > > What's "nyan"? Are there other variants of "big" other than "nyan"? Nyan is the name for our Tegra124 reference platform. Big is derived from this and there are other variants of Nyan other than Big. >> + serial@0,70006000 { >> + status = "okay"; >> + }; > > We've started to annotate some of these nodes in other DTS files to make > it easier for people to match them to connectors on the board (or the > schematics). This isn't necessarily important for things like PWM, since > their use is fairly obvious and usually in-kernel only (with perhaps an > exception of a PWM routed to some expansion header on some development > board). For generic interfaces it's good to know what they map to on the > device. > > Is this serial available as an accessible connector? Or is it some debug > serial that's only available on a (non-equipped) header on the board? There is a debug connector on the board which provides the serial lines. It is similar to Venice2, but in a different form factor. >> + i2c@0,7000c400 { >> + status = "okay"; >> + clock-frequency = <100000>; >> + }; >> + >> + i2c@0,7000c500 { >> + status = "okay"; >> + clock-frequency = <400000>; >> + >> + tpm@20 { >> + compatible = "infineon,slb9645tt"; >> + reg = <0x20>; >> + }; > > I presume this is the TPM that you said isn't reset on reboot? Do you > know the reason for why it isn't being reset? What's needed to reset > this module? I assume it's something that can (and will eventually) be > fixed? Tegra SoCs are normally reset via the PMC, however that does not reset any external peripherals. In order to reset the TPM at the same time as the SoC, the GPIO I5 must be driven low. Something like the gpio-poweroff driver, but instead for restart could be used to do this. >> + battery: sbs-battery@b { >> + compatible = "sbs,sbs-battery"; >> + reg = <0xb>; >> + sbs,i2c-retry-count = <2>; >> + sbs,poll-retry-count = <10>; >> + power-supplies = <&charger>; > > The sbs-battery binding doesn't define a power-supplies property. It does, but it's not specific to sbs-battery. All power supplies have an optional power-supplies property, see Documentation/devicetree/bindings/power_supply/power_supply.txt. ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree 2014-08-13 8:53 ` Thierry Reding 2014-08-13 16:23 ` Andrew Bresticker @ 2014-08-13 16:51 ` Olof Johansson [not found] ` <CAOesGMg2uZ8-ypeuSXJoSN3mz6jBjNwLbTo9EiXOf2D7iVCfiQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2014-08-13 16:51 ` Stephen Warren 2014-08-13 18:42 ` Dylan Reid 3 siblings, 1 reply; 28+ messages in thread From: Olof Johansson @ 2014-08-13 16:51 UTC (permalink / raw) To: Thierry Reding Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Wed, Aug 13, 2014 at 1:53 AM, Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> processor and is similar to the Venice2 reference platform. >> >> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> and work on the 1366x768 models. I haven't tried on the HD systems >> yet. > > Presumably the HD systems will have a different compatible? Is it only > the panel that's different or are there other changes? > >> There is also an issue on reboot because the TPM isn't reset. It will >> cause the stock firmware to enter recovery mode. This can be worked >> around by an EC-reset, press refresh and power at the same time. > > It's not clear to me what exactly this implies. Does it mean the system > won't boot unless you manually press "refresh" and "power"? Are those > keyboard buttons or keys on some debug board? > >> diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts >> new file mode 100644 >> index 0000000..aa0cd9f >> --- /dev/null >> +++ b/arch/arm/boot/dts/tegra124-big.dts >> @@ -0,0 +1,1137 @@ >> +/dts-v1/; >> + >> +#include <dt-bindings/input/input.h> >> +#include "tegra124.dtsi" >> + >> +/ { >> + model = "Google Big"; > > Perhaps this should at least mention that it's the Acer Chromebook 13. > Otherwise this could just as well be some random development board. > >> + compatible = "google,nyan-big", "nvidia,tegra124"; > > What's "nyan"? Are there other variants of "big" other than "nyan"? > >> + pinmux: pinmux@0,70000868 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinmux_default>; >> + >> + pinmux_default: common { >> + dap_mclk1_pw4 { >> + nvidia,pins = "dap_mclk1_pw4"; >> + nvidia,function = "extperiph1"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; > > Stephen proposed a patch not so long ago that removes the static pinmux > settings from DTS files[0]. I'd expect he'll have objections to this DTS > providing the static settings. > > The assumption with that patch is that the bootloader will have to set > up the entire pinmux anyway (to prevent conflicting settings), therefore > there'd be no need to do it in the kernel. Is this something that your > bootloader already does (or could be modified to do)? It's extra work to switch it over since the assumption is brand new. It's something we can consider for future platforms but Stephen dropped that patch like a bomb from a blue sky _after_ the final versions of firmware had been cut -- or more importantly, tested. So, we should have this in the kernel at this time. We've always been developing the linux kernel on embedded platforms with the mindset that firmware will usually get things wrong at some point, so the safe thing is to not make assumptions about how it has configured the hardware and do most of it from scratch in the kernel. It's how we have handled all tegra pinmux up until now, and doing a 180-degree turn on this now, when there has been no _new_ concerns that caused this, seems like a complication that is just throwing everybody in a loop. The same concerns about conflicting pinmux settings surely exists on any platform that does muxing. Tegra isn't unique in this way, so I wonder what is causing the need to remove this functionality from the kernel? I'll be happy to discuss this more off-list w.r.t. future projects that we can cut over to rely more on firmware pinmux, but the public mailing list is not the right place for that. -Olof ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <CAOesGMg2uZ8-ypeuSXJoSN3mz6jBjNwLbTo9EiXOf2D7iVCfiQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <CAOesGMg2uZ8-ypeuSXJoSN3mz6jBjNwLbTo9EiXOf2D7iVCfiQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-08-13 16:57 ` Stephen Warren 0 siblings, 0 replies; 28+ messages in thread From: Stephen Warren @ 2014-08-13 16:57 UTC (permalink / raw) To: Olof Johansson, Thierry Reding Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 08/13/2014 10:51 AM, Olof Johansson wrote: > On Wed, Aug 13, 2014 at 1:53 AM, Thierry Reding > <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: >> On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>> processor and is similar to the Venice2 reference platform. >>> >>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>> and work on the 1366x768 models. I haven't tried on the HD systems >>> yet. >> >> Presumably the HD systems will have a different compatible? Is it only >> the panel that's different or are there other changes? >> >>> There is also an issue on reboot because the TPM isn't reset. It will >>> cause the stock firmware to enter recovery mode. This can be worked >>> around by an EC-reset, press refresh and power at the same time. >> >> It's not clear to me what exactly this implies. Does it mean the system >> won't boot unless you manually press "refresh" and "power"? Are those >> keyboard buttons or keys on some debug board? >> >>> diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts >>> new file mode 100644 >>> index 0000000..aa0cd9f >>> --- /dev/null >>> +++ b/arch/arm/boot/dts/tegra124-big.dts >>> @@ -0,0 +1,1137 @@ >>> +/dts-v1/; >>> + >>> +#include <dt-bindings/input/input.h> >>> +#include "tegra124.dtsi" >>> + >>> +/ { >>> + model = "Google Big"; >> >> Perhaps this should at least mention that it's the Acer Chromebook 13. >> Otherwise this could just as well be some random development board. >> >>> + compatible = "google,nyan-big", "nvidia,tegra124"; >> >> What's "nyan"? Are there other variants of "big" other than "nyan"? >> >>> + pinmux: pinmux@0,70000868 { >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&pinmux_default>; >>> + >>> + pinmux_default: common { >>> + dap_mclk1_pw4 { >>> + nvidia,pins = "dap_mclk1_pw4"; >>> + nvidia,function = "extperiph1"; >>> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >>> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >>> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >>> + }; >> >> Stephen proposed a patch not so long ago that removes the static pinmux >> settings from DTS files[0]. I'd expect he'll have objections to this DTS >> providing the static settings. >> >> The assumption with that patch is that the bootloader will have to set >> up the entire pinmux anyway (to prevent conflicting settings), therefore >> there'd be no need to do it in the kernel. Is this something that your >> bootloader already does (or could be modified to do)? > > It's extra work to switch it over since the assumption is brand new. > It's something we can consider for future platforms but Stephen > dropped that patch like a bomb from a blue sky _after_ the final > versions of firmware had been cut -- or more importantly, tested. So, > we should have this in the kernel at this time. > > We've always been developing the linux kernel on embedded platforms > with the mindset that firmware will usually get things wrong at some > point, so the safe thing is to not make assumptions about how it has > configured the hardware and do most of it from scratch in the kernel. > It's how we have handled all tegra pinmux up until now, and doing a > 180-degree turn on this now, when there has been no _new_ concerns > that caused this, seems like a complication that is just throwing > everybody in a loop. > > The same concerns about conflicting pinmux settings surely exists on > any platform that does muxing. Tegra isn't unique in this way, so I > wonder what is causing the need to remove this functionality from the > kernel? It depends on the HW design, so it's quite possible HW-specific, or only affects a subset of HW with pinmux. It's quite possible for pinmux HW to allow each pin/pad/... to support 1 of N signals, yet only allow a particular signal to be routed to 1 particular pin/pad. For such HW, there can never be conflicts, and hence there's no issue. It's also possible that pinmux HW that allows a particular signal to be routed to various different pins/pads is designed in such a way that conflicts aren't possible, or aren't an issue. The registers could be designed to invert their sense, so that each signal gets a register saying where it's routed. Alternatively, the HW could have specific interlocks implemented so that if conflicts are programmed into the registers, the HW resolves them based on some priority, so that even if you don't get what you asked for, at least you get something well-defined. Admittedly the HW cost associated with either of these options is low. I think the only way to move forward on not considering firmware buggy is to enforce it not to be, and to do that we have to draw a line in the sand at some point. I strongly want to make that point Tegra124 and later for upstream support. Finally note while the patch in question was new to upstream and may seem like a bomb there, it's *absolutely* not something new in other contexts. However, as you say we can discuss this elsewhere. ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree 2014-08-13 8:53 ` Thierry Reding 2014-08-13 16:23 ` Andrew Bresticker 2014-08-13 16:51 ` Olof Johansson @ 2014-08-13 16:51 ` Stephen Warren [not found] ` <53EB9786.6010809-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2014-08-13 18:42 ` Dylan Reid 3 siblings, 1 reply; 28+ messages in thread From: Stephen Warren @ 2014-08-13 16:51 UTC (permalink / raw) To: Thierry Reding, Dylan Reid Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, abrestic-F7+t8E8rja9g9hUCZPvPmw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, olof-nZhT3qVonbNeoWH0uzbU5w On 08/13/2014 02:53 AM, Thierry Reding wrote: > On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> processor and is similar to the Venice2 reference platform. >> >> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> and work on the 1366x768 models. I haven't tried on the HD systems >> yet. > > Presumably the HD systems will have a different compatible? Is it only > the panel that's different or are there other changes? Yes, we definitely need to plan ahead for the different SKUs. I assume we'll have different board names for each board, which then translates int DT filenames and U-Boot/cbootimage-configs/tegra-uboot-flasher board >> There is also an issue on reboot because the TPM isn't reset. It will >> cause the stock firmware to enter recovery mode. This can be worked >> around by an EC-reset, press refresh and power at the same time. > > It's not clear to me what exactly this implies. Does it mean the system > won't boot unless you manually press "refresh" and "power"? Are those > keyboard buttons or keys on some debug board? > >> diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts >> +/ { >> + model = "Google Big"; > > Perhaps this should at least mention that it's the Acer Chromebook 13. > Otherwise this could just as well be some random development board. > >> + compatible = "google,nyan-big", "nvidia,tegra124"; > > What's "nyan"? Are there other variants of "big" other than "nyan"? I thought this board was known as Nike? >> + pinmux: pinmux@0,70000868 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinmux_default>; >> + >> + pinmux_default: common { >> + dap_mclk1_pw4 { >> + nvidia,pins = "dap_mclk1_pw4"; >> + nvidia,function = "extperiph1"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; > > Stephen proposed a patch not so long ago that removes the static pinmux > settings from DTS files[0]. I'd expect he'll have objections to this DTS > providing the static settings. > > The assumption with that patch is that the bootloader will have to set > up the entire pinmux anyway (to prevent conflicting settings), therefore > there'd be no need to do it in the kernel. Is this something that your > bootloader already does (or could be modified to do)? > > [0]: http://patchwork.ozlabs.org/patch/363222/ Yes, definitely I want to remove the pinmux from the kernel, since the HW design implies that the bootloader must set this up completely. IIRC, the bootloader on this device doesn't. However, the workaround was that the U-Boot that the firmware chain-loads in order to load Linux (which IIRC is mandatory for non-Google kernels?) would do this setup before booting the kernel. ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <53EB9786.6010809-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <53EB9786.6010809-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2014-08-13 16:55 ` Olof Johansson 2014-08-13 17:04 ` Andrew Bresticker 1 sibling, 0 replies; 28+ messages in thread From: Olof Johansson @ 2014-08-13 16:55 UTC (permalink / raw) To: Stephen Warren Cc: Thierry Reding, Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Wed, Aug 13, 2014 at 9:51 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 08/13/2014 02:53 AM, Thierry Reding wrote: >> >> On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >>> >>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>> processor and is similar to the Venice2 reference platform. >>> >>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>> and work on the 1366x768 models. I haven't tried on the HD systems >>> yet. >> >> >> Presumably the HD systems will have a different compatible? Is it only >> the panel that's different or are there other changes? > > > Yes, we definitely need to plan ahead for the different SKUs. I assume we'll > have different board names for each board, which then translates int DT > filenames and U-Boot/cbootimage-configs/tegra-uboot-flasher board > > >>> There is also an issue on reboot because the TPM isn't reset. It will >>> cause the stock firmware to enter recovery mode. This can be worked >>> around by an EC-reset, press refresh and power at the same time. >> >> >> It's not clear to me what exactly this implies. Does it mean the system >> won't boot unless you manually press "refresh" and "power"? Are those >> keyboard buttons or keys on some debug board? >> >>> diff --git a/arch/arm/boot/dts/tegra124-big.dts >>> b/arch/arm/boot/dts/tegra124-big.dts > > >>> +/ { >>> + model = "Google Big"; >> >> >> Perhaps this should at least mention that it's the Acer Chromebook 13. >> Otherwise this could just as well be some random development board. >> >>> + compatible = "google,nyan-big", "nvidia,tegra124"; >> >> >> What's "nyan"? Are there other variants of "big" other than "nyan"? > > > I thought this board was known as Nike? > > >>> + pinmux: pinmux@0,70000868 { >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&pinmux_default>; >>> + >>> + pinmux_default: common { >>> + dap_mclk1_pw4 { >>> + nvidia,pins = "dap_mclk1_pw4"; >>> + nvidia,function = "extperiph1"; >>> + nvidia,enable-input = >>> <TEGRA_PIN_DISABLE>; >>> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >>> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >>> + }; >> >> >> Stephen proposed a patch not so long ago that removes the static pinmux >> settings from DTS files[0]. I'd expect he'll have objections to this DTS >> providing the static settings. >> >> The assumption with that patch is that the bootloader will have to set >> up the entire pinmux anyway (to prevent conflicting settings), therefore >> there'd be no need to do it in the kernel. Is this something that your >> bootloader already does (or could be modified to do)? >> >> [0]: http://patchwork.ozlabs.org/patch/363222/ > > > Yes, definitely I want to remove the pinmux from the kernel, since the HW > design implies that the bootloader must set this up completely. > > IIRC, the bootloader on this device doesn't. However, the workaround was > that the U-Boot that the firmware chain-loads in order to load Linux (which > IIRC is mandatory for non-Google kernels?) would do this setup before > booting the kernel. You can wrap a regular mainline kernel with the verified boot block and load it without u-boot. I do it all the time on x86, ARM is no different. The main reason for using u-boot is so that you get a command line, can do network-based booting, bootloader configuration scripts, and so on. So, it's not a useful workaround, unfortunately. :( -Olof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <53EB9786.6010809-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2014-08-13 16:55 ` Olof Johansson @ 2014-08-13 17:04 ` Andrew Bresticker [not found] ` <CAL1qeaGxcp4okVTYCMj0zMh-4HzsGLBvngv0+A1m8o3sZPDj2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 1 sibling, 1 reply; 28+ messages in thread From: Andrew Bresticker @ 2014-08-13 17:04 UTC (permalink / raw) To: Stephen Warren Cc: Thierry Reding, Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On Wed, Aug 13, 2014 at 9:51 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 08/13/2014 02:53 AM, Thierry Reding wrote: >> >> On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >>> >>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>> processor and is similar to the Venice2 reference platform. >>> >>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>> and work on the 1366x768 models. I haven't tried on the HD systems >>> yet. >> >> >> Presumably the HD systems will have a different compatible? Is it only >> the panel that's different or are there other changes? > > > Yes, we definitely need to plan ahead for the different SKUs. I assume we'll > have different board names for each board, which then translates int DT > filenames and U-Boot/cbootimage-configs/tegra-uboot-flasher board The firmware does not differentiate between the HD and non-HD boards, so it will look for the same compatible string. As I mentioned in my response to Thierry, we'd need to parse the EDID to figure out which panel is being used. >>> + compatible = "google,nyan-big", "nvidia,tegra124"; >> >> >> What's "nyan"? Are there other variants of "big" other than "nyan"? > > > I thought this board was known as Nike? Nike is Acer's name for the board. We call Tegra124-based boards Nyan-${variant}. ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <CAL1qeaGxcp4okVTYCMj0zMh-4HzsGLBvngv0+A1m8o3sZPDj2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <CAL1qeaGxcp4okVTYCMj0zMh-4HzsGLBvngv0+A1m8o3sZPDj2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-08-13 17:12 ` Stephen Warren [not found] ` <53EB9C61.1070406-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 0 siblings, 1 reply; 28+ messages in thread From: Stephen Warren @ 2014-08-13 17:12 UTC (permalink / raw) To: Andrew Bresticker Cc: Thierry Reding, Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On 08/13/2014 11:04 AM, Andrew Bresticker wrote: > On Wed, Aug 13, 2014 at 9:51 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: >> On 08/13/2014 02:53 AM, Thierry Reding wrote: >>> >>> On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >>>> >>>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>>> processor and is similar to the Venice2 reference platform. >>>> >>>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>>> and work on the 1366x768 models. I haven't tried on the HD systems >>>> yet. >>> >>> >>> Presumably the HD systems will have a different compatible? Is it only >>> the panel that's different or are there other changes? >> >> >> Yes, we definitely need to plan ahead for the different SKUs. I assume we'll >> have different board names for each board, which then translates int DT >> filenames and U-Boot/cbootimage-configs/tegra-uboot-flasher board > > The firmware does not differentiate between the HD and non-HD boards, > so it will look for the same compatible string. As I mentioned in my > response to Thierry, we'd need to parse the EDID to figure out which > panel is being used. Well, that's if we do it at run-time. We could just have a separate DT per SKU, couldn't we? ^ permalink raw reply [flat|nested] 28+ messages in thread
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* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <53EB9C61.1070406-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2014-08-13 17:17 ` Andrew Bresticker 0 siblings, 0 replies; 28+ messages in thread From: Andrew Bresticker @ 2014-08-13 17:17 UTC (permalink / raw) To: Stephen Warren Cc: Thierry Reding, Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On Wed, Aug 13, 2014 at 10:12 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 08/13/2014 11:04 AM, Andrew Bresticker wrote: >> >> On Wed, Aug 13, 2014 at 9:51 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> >> wrote: >>> >>> On 08/13/2014 02:53 AM, Thierry Reding wrote: >>>> >>>> >>>> On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >>>>> >>>>> >>>>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>>>> processor and is similar to the Venice2 reference platform. >>>>> >>>>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>>>> and work on the 1366x768 models. I haven't tried on the HD systems >>>>> yet. >>>> >>>> >>>> >>>> Presumably the HD systems will have a different compatible? Is it only >>>> the panel that's different or are there other changes? >>> >>> >>> >>> Yes, we definitely need to plan ahead for the different SKUs. I assume >>> we'll >>> have different board names for each board, which then translates int DT >>> filenames and U-Boot/cbootimage-configs/tegra-uboot-flasher board >> >> >> The firmware does not differentiate between the HD and non-HD boards, >> so it will look for the same compatible string. As I mentioned in my >> response to Thierry, we'd need to parse the EDID to figure out which >> panel is being used. > > > Well, that's if we do it at run-time. We could just have a separate DT per > SKU, couldn't we? Oh right - yes, that would work. ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree 2014-08-13 8:53 ` Thierry Reding ` (2 preceding siblings ...) 2014-08-13 16:51 ` Stephen Warren @ 2014-08-13 18:42 ` Dylan Reid 3 siblings, 0 replies; 28+ messages in thread From: Dylan Reid @ 2014-08-13 18:42 UTC (permalink / raw) To: Thierry Reding Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org On Wed, Aug 13, 2014 at 1:53 AM, Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > On Tue, Aug 12, 2014 at 06:56:07PM -0700, Dylan Reid wrote: >> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> processor and is similar to the Venice2 reference platform. >> >> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> and work on the 1366x768 models. I haven't tried on the HD systems >> yet. > > Presumably the HD systems will have a different compatible? Is it only > the panel that's different or are there other changes? > >> There is also an issue on reboot because the TPM isn't reset. It will >> cause the stock firmware to enter recovery mode. This can be worked >> around by an EC-reset, press refresh and power at the same time. > > It's not clear to me what exactly this implies. Does it mean the system > won't boot unless you manually press "refresh" and "power"? Are those > keyboard buttons or keys on some debug board? > >> diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts >> new file mode 100644 >> index 0000000..aa0cd9f >> --- /dev/null >> +++ b/arch/arm/boot/dts/tegra124-big.dts >> @@ -0,0 +1,1137 @@ >> +/dts-v1/; >> + >> +#include <dt-bindings/input/input.h> >> +#include "tegra124.dtsi" >> + >> +/ { >> + model = "Google Big"; > > Perhaps this should at least mention that it's the Acer Chromebook 13. > Otherwise this could just as well be some random development board. > >> + compatible = "google,nyan-big", "nvidia,tegra124"; > > What's "nyan"? Are there other variants of "big" other than "nyan"? > >> + pinmux: pinmux@0,70000868 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinmux_default>; >> + >> + pinmux_default: common { >> + dap_mclk1_pw4 { >> + nvidia,pins = "dap_mclk1_pw4"; >> + nvidia,function = "extperiph1"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; > > Stephen proposed a patch not so long ago that removes the static pinmux > settings from DTS files[0]. I'd expect he'll have objections to this DTS > providing the static settings. > > The assumption with that patch is that the bootloader will have to set > up the entire pinmux anyway (to prevent conflicting settings), therefore > there'd be no need to do it in the kernel. Is this something that your > bootloader already does (or could be modified to do)? > > [0]: http://patchwork.ozlabs.org/patch/363222/ Thanks for looking Thierry, Per later discussion I'll leave this for now. The firmware shipping on the device doesn't handle this but we've already made the changes that fix that for later products. > >> + serial@0,70006000 { >> + status = "okay"; >> + }; > > We've started to annotate some of these nodes in other DTS files to make > it easier for people to match them to connectors on the board (or the > schematics). This isn't necessarily important for things like PWM, since > their use is fairly obvious and usually in-kernel only (with perhaps an > exception of a PWM routed to some expansion header on some development > board). For generic interfaces it's good to know what they map to on the > device. > > Is this serial available as an accessible connector? Or is it some debug > serial that's only available on a (non-equipped) header on the board? comment added. > >> + i2c@0,7000c400 { >> + status = "okay"; >> + clock-frequency = <100000>; >> + }; >> + >> + i2c@0,7000c500 { >> + status = "okay"; >> + clock-frequency = <400000>; >> + >> + tpm@20 { >> + compatible = "infineon,slb9645tt"; >> + reg = <0x20>; >> + }; > > I presume this is the TPM that you said isn't reset on reboot? Do you > know the reason for why it isn't being reset? What's needed to reset > this module? I assume it's something that can (and will eventually) be > fixed? > >> + cros_ec: cros-ec@0 { >> + compatible = "google,cros-ec-spi"; >> + spi-max-frequency = <3000000>; >> + interrupt-parent = <&gpio>; >> + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; >> + reg = <0>; >> + >> + google,cros-ec-spi-msg-delay = <2000>; >> + >> + i2c-tunnel { >> + compatible = "google,cros-ec-i2c-tunnel"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + google,remote-bus = <0>; >> + >> + charger: bq24735@9 { >> + compatible = "ti,bq24735"; >> + reg = <0x9>; >> + interrupt-parent = <&gpio>; >> + interrupts = <TEGRA_GPIO(J, 0) >> + GPIO_ACTIVE_HIGH>; >> + ti,ac-detect-gpios = <&gpio >> + TEGRA_GPIO(J, 0) >> + GPIO_ACTIVE_HIGH>; > > Given this, I wonder how useful the 80-chars limit is for DTS files... > >> + battery: sbs-battery@b { >> + compatible = "sbs,sbs-battery"; >> + reg = <0xb>; >> + sbs,i2c-retry-count = <2>; >> + sbs,poll-retry-count = <10>; >> + power-supplies = <&charger>; > > The sbs-battery binding doesn't define a power-supplies property. > >> + spi@0,7000da00 { >> + status = "okay"; >> + spi-max-frequency = <25000000>; >> + spi-flash@0 { > > I think it's customary to separate the properties and child nodes using > a blank line. > > Also, and I know other DTS files contain the same, I think spi-flash is > kind of redundant, since it's a child of an SPI node. both changed. > >> + compatible = "winbond,w25q32dw"; >> + reg = <0>; >> + spi-max-frequency = <25000000>; > > Isn't the maximum frequency inherited from the parent? yes, removed the extra setting. > >> + sdhci@0,700b0000 { >> + status = "okay"; >> + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; >> + bus-width = <4>; >> + no-1-8-v; >> + non-removable; >> + }; >> + >> + sdhci@0,700b0400 { >> + status = "okay"; >> + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; >> + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; >> + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; >> + bus-width = <4>; >> + no-1-8-v; >> + vqmmc-supply = <&vddio_sdmmc3>; >> + }; >> + >> + sdhci@0,700b0600 { >> + status = "okay"; >> + bus-width = <8>; >> + no-1-8-v; >> + non-removable; >> + }; > > For these it might be good to know which is the external one (I assume > there is one). I'm guessing sdhc@0,700b0000 is eMMC because it is marked > non-removable, but a comment would be good to make it explicit. > >> + usb@0,7d000000 { >> + status = "okay"; >> + }; >> + >> + usb-phy@0,7d000000 { >> + status = "okay"; >> + vbus-supply = <&vdd_usb1_vbus>; >> + }; >> + >> + usb@0,7d004000 { >> + status = "okay"; >> + }; >> + >> + usb-phy@0,7d004000 { >> + status = "okay"; >> + vbus-supply = <&vdd_run_cam>; >> + }; >> + >> + usb@0,7d008000 { >> + status = "okay"; >> + }; >> + >> + usb-phy@0,7d008000 { >> + status = "okay"; >> + vbus-supply = <&vdd_usb3_vbus>; >> + }; > > Similarly for these. I added comments to each sdhci and usb block about where it is on the device. > >> + >> + backlight: backlight { >> + compatible = "pwm-backlight"; >> + >> + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; >> + power-supply = <&vdd_led>; >> + pwms = <&pwm 1 1000000>; >> + >> + default-brightness-level = <224>; >> + brightness-levels = >> + < 0 1 2 3 4 5 6 7 >> + 8 9 10 11 12 13 14 15 >> + 16 17 18 19 20 21 22 23 >> + 24 25 26 27 28 29 30 31 >> + 32 33 34 35 36 37 38 39 >> + 40 41 42 43 44 45 46 47 >> + 48 49 50 51 52 53 54 55 >> + 56 57 58 59 60 61 62 63 >> + 64 65 66 67 68 69 70 71 >> + 72 73 74 75 76 77 78 79 >> + 80 81 82 83 84 85 86 87 >> + 88 89 90 91 92 93 94 95 >> + 96 97 98 99 100 101 102 103 >> + 104 105 106 107 108 109 110 111 >> + 112 113 114 115 116 117 118 119 >> + 120 121 122 123 124 125 126 127 >> + 128 129 130 131 132 133 134 135 >> + 136 137 138 139 140 141 142 143 >> + 144 145 146 147 148 149 150 151 >> + 152 153 154 155 156 157 158 159 >> + 160 161 162 163 164 165 166 167 >> + 168 169 170 171 172 173 174 175 >> + 176 177 178 179 180 181 182 183 >> + 184 185 186 187 188 189 190 191 >> + 192 193 194 195 196 197 198 199 >> + 200 201 202 203 204 205 206 207 >> + 208 209 210 211 212 213 214 215 >> + 216 217 218 219 220 221 222 223 >> + 224 225 226 227 228 229 230 231 >> + 232 233 234 235 236 237 238 239 >> + 240 241 242 243 244 245 246 247 >> + 248 249 250 251 252 253 254 255 >> + 256>; > > I'm curious, does ChromeOS really need 257 levels of brightness? I don't > think I've seen a consumer product that supports more than a dozen > levels. need is maybe a strong word, but 100 of them are exposed to the user and I think the automatic adjustment uses all of them. > >> + panel: panel { >> + compatible = "auo,b133xtn01", "simple-panel"; > > There was a discussion a few days ago about this, and "simple-panel" > really isn't useful in the list of compatible strings. I already have a > patch queued up that removes that entry from all existing device trees > and also gets rid of the OF match table entry in the panel-simple > driver. Removed. > > Thierry ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <1407894967-18300-1-git-send-email-dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> 2014-08-13 8:53 ` Thierry Reding @ 2014-08-13 17:10 ` Stephen Warren [not found] ` <53EB9BF0.9010002-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2015-01-13 17:49 ` Tomeu Vizoso 2015-01-19 9:01 ` Tomeu Vizoso 3 siblings, 1 reply; 28+ messages in thread From: Stephen Warren @ 2014-08-13 17:10 UTC (permalink / raw) To: Dylan Reid Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w, abrestic-F7+t8E8rja9g9hUCZPvPmw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, olof-nZhT3qVonbNeoWH0uzbU5w On 08/12/2014 07:56 PM, Dylan Reid wrote: > The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 > processor and is similar to the Venice2 reference platform. > > The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested > and work on the 1366x768 models. I haven't tried on the HD systems > yet. > > WiFi does not yet work, it needs at least some PMIC changes to enable > the 32k clock. > > The elan trackpad is not yet functional but hopefully will be soon as > there are patches under review. > > There is also an issue on reboot because the TPM isn't reset. It will > cause the stock firmware to enter recovery mode. This can be worked > around by an EC-reset, press refresh and power at the same time. > diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts I think we need to include the SKU name in the filename and compatible value below, or at least plan out that for other SKUs, we'll add the SKU name on. > +/ { > + model = "Google Big"; > + compatible = "google,nyan-big", "nvidia,tegra124"; I think it'd be more user-friendly if the filename and compatible value more obviously tied to the end-user-visible product name. > + gpio-keys { > + compatible = "gpio-keys"; > + > + lid { > + label = "Lid"; > + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; > + linux,input-type = <5>; > + linux,code = <0>; Aren't there #defines for the 5 and 0 there? > + sound { > + compatible = "nvidia,tegra-audio-max98090-venice2", > + "nvidia,tegra-audio-max98090"; > + nvidia,model = "NVIDIA Tegra Venice2"; Those strings should all use the same board name as the filename, compatible value, and model of the root node. Based on the content in your patch, I would expect: compatible = "nvidia,tegra-audio-max98090-big", "nvidia,tegra-audio-max98090"; nvidia,model = "Google Big"; In particular, nvidia,model is used to index into /var/lib/alsa/asound.state by name, so it needs to be unique for each board. > + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7) > + GPIO_ACTIVE_HIGH>; That property doesn't (yet) exist in the binding/code upstream. It could obviously be added. ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <53EB9BF0.9010002-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <53EB9BF0.9010002-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2014-08-13 17:23 ` Olof Johansson [not found] ` <CAOesGMhAzx==sXnHBg4dhAtO3=JP-s-MmzujskctA=7OUC0uRg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2014-08-13 19:07 ` Dylan Reid 1 sibling, 1 reply; 28+ messages in thread From: Olof Johansson @ 2014-08-13 17:23 UTC (permalink / raw) To: Stephen Warren Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Wed, Aug 13, 2014 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 08/12/2014 07:56 PM, Dylan Reid wrote: >> >> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> processor and is similar to the Venice2 reference platform. >> >> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> and work on the 1366x768 models. I haven't tried on the HD systems >> yet. >> >> WiFi does not yet work, it needs at least some PMIC changes to enable >> the 32k clock. >> >> The elan trackpad is not yet functional but hopefully will be soon as >> there are patches under review. >> >> There is also an issue on reboot because the TPM isn't reset. It will >> cause the stock firmware to enter recovery mode. This can be worked >> around by an EC-reset, press refresh and power at the same time. > > >> diff --git a/arch/arm/boot/dts/tegra124-big.dts >> b/arch/arm/boot/dts/tegra124-big.dts > > > I think we need to include the SKU name in the filename and compatible value > below, or at least plan out that for other SKUs, we'll add the SKU name on. > > >> +/ { >> + model = "Google Big"; >> + compatible = "google,nyan-big", "nvidia,tegra124"; > > > I think it'd be more user-friendly if the filename and compatible value more > obviously tied to the end-user-visible product name. We didn't prefix the reference platform on the very first one we shipped (snow), but for the peach platforms we used peach-pit and peach-pi. Those had different SoCs inside (albeit very similar ones), so there was a reason for separate DTS files. Here, we should probably prefix with nyan (so tegra124-nyan-big.dts). Users have shown themselves to be quite happy to use the internal names, they also tend to be less confusing (since we can't rely on the vendor to rename the product when the internals change, so we would need a separate namespace anyway). What we did on pit/pi was to add a more-specific revision of the hardware in front. That was more about dealing with various generations of the hardware though (as components sometimes change over the lifetime production). Here it's more about the basic SKU/feature set (panel size, touch screen). I suspect we'll do a big-touch.dts that just includes this and appends the TS device. For the panel sizes, do we need the specifics in the DT instead of via EDID? Do we really need to describe the exact panel in the DTS? Note that panels are pretty common to change over the production run of a product too, second sourcing, etc. Model could be changed to "Acer Chromebook 13", I suppose. In the past we've used "Google Peach Pit", "Google Snow". No user has complained yet about that. -Olof ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <CAOesGMhAzx==sXnHBg4dhAtO3=JP-s-MmzujskctA=7OUC0uRg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <CAOesGMhAzx==sXnHBg4dhAtO3=JP-s-MmzujskctA=7OUC0uRg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-08-13 17:31 ` Stephen Warren [not found] ` <53EBA0ED.30607-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 0 siblings, 1 reply; 28+ messages in thread From: Stephen Warren @ 2014-08-13 17:31 UTC (permalink / raw) To: Olof Johansson Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 08/13/2014 11:23 AM, Olof Johansson wrote: > On Wed, Aug 13, 2014 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: >> On 08/12/2014 07:56 PM, Dylan Reid wrote: >>> >>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>> processor and is similar to the Venice2 reference platform. >>> >>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>> and work on the 1366x768 models. I haven't tried on the HD systems >>> yet. >>> >>> WiFi does not yet work, it needs at least some PMIC changes to enable >>> the 32k clock. >>> >>> The elan trackpad is not yet functional but hopefully will be soon as >>> there are patches under review. >>> >>> There is also an issue on reboot because the TPM isn't reset. It will >>> cause the stock firmware to enter recovery mode. This can be worked >>> around by an EC-reset, press refresh and power at the same time. >> >> >>> diff --git a/arch/arm/boot/dts/tegra124-big.dts >>> b/arch/arm/boot/dts/tegra124-big.dts >> >> >> I think we need to include the SKU name in the filename and compatible value >> below, or at least plan out that for other SKUs, we'll add the SKU name on. >> >> >>> +/ { >>> + model = "Google Big"; >>> + compatible = "google,nyan-big", "nvidia,tegra124"; >> >> >> I think it'd be more user-friendly if the filename and compatible value more >> obviously tied to the end-user-visible product name. > > We didn't prefix the reference platform on the very first one we > shipped (snow), but for the peach platforms we used peach-pit and > peach-pi. Those had different SoCs inside (albeit very similar ones), > so there was a reason for separate DTS files. > > Here, we should probably prefix with nyan (so tegra124-nyan-big.dts). > Users have shown themselves to be quite happy to use the internal > names, they also tend to be less confusing (since we can't rely on the > vendor to rename the product when the internals change, so we would > need a separate namespace anyway). I can see that the vendor might change the internals without changing the product name. That kind of thing happens too frequently across all kinds of products. So, there are certainly disadvantages using consumer marketing names here. Presumably though the name "big" would no longer apply to any modified HW? Hence, I can't understand the need to say "nyan-big" rather than just "big". Is "nyan-" really needed to fully qualify the name? Also, the board isn't a Nyan, albeit the design may have been strongly derived from the reference board named Nyan. > What we did on pit/pi was to add a more-specific revision of the > hardware in front. That was more about dealing with various > generations of the hardware though (as components sometimes change > over the lifetime production). Here it's more about the basic > SKU/feature set (panel size, touch screen). I suspect we'll do a > big-touch.dts that just includes this and appends the TS device. > > For the panel sizes, do we need the specifics in the DT instead of via > EDID? Do we really need to describe the exact panel in the DTS? Note > that panels are pretty common to change over the production run of a > product too, second sourcing, etc. > > Model could be changed to "Acer Chromebook 13", I suppose. In the past > we've used "Google Peach Pit", "Google Snow". No user has complained > yet about that. ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <53EBA0ED.30607-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <53EBA0ED.30607-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2014-08-13 17:37 ` Olof Johansson [not found] ` <CAOesGMgeLbuURwA1VVxkLp=vH9PB_VdUHFJthH=ae-_ZDVYyAA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 28+ messages in thread From: Olof Johansson @ 2014-08-13 17:37 UTC (permalink / raw) To: Stephen Warren Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Wed, Aug 13, 2014 at 10:31 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 08/13/2014 11:23 AM, Olof Johansson wrote: >> >> On Wed, Aug 13, 2014 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> >> wrote: >>> >>> On 08/12/2014 07:56 PM, Dylan Reid wrote: >>>> >>>> >>>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>>> processor and is similar to the Venice2 reference platform. >>>> >>>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>>> and work on the 1366x768 models. I haven't tried on the HD systems >>>> yet. >>>> >>>> WiFi does not yet work, it needs at least some PMIC changes to enable >>>> the 32k clock. >>>> >>>> The elan trackpad is not yet functional but hopefully will be soon as >>>> there are patches under review. >>>> >>>> There is also an issue on reboot because the TPM isn't reset. It will >>>> cause the stock firmware to enter recovery mode. This can be worked >>>> around by an EC-reset, press refresh and power at the same time. >>> >>> >>> >>>> diff --git a/arch/arm/boot/dts/tegra124-big.dts >>>> b/arch/arm/boot/dts/tegra124-big.dts >>> >>> >>> >>> I think we need to include the SKU name in the filename and compatible >>> value >>> below, or at least plan out that for other SKUs, we'll add the SKU name >>> on. >>> >>> >>>> +/ { >>>> + model = "Google Big"; >>>> + compatible = "google,nyan-big", "nvidia,tegra124"; >>> >>> >>> >>> I think it'd be more user-friendly if the filename and compatible value >>> more >>> obviously tied to the end-user-visible product name. >> >> >> We didn't prefix the reference platform on the very first one we >> shipped (snow), but for the peach platforms we used peach-pit and >> peach-pi. Those had different SoCs inside (albeit very similar ones), >> so there was a reason for separate DTS files. >> >> Here, we should probably prefix with nyan (so tegra124-nyan-big.dts). >> Users have shown themselves to be quite happy to use the internal >> names, they also tend to be less confusing (since we can't rely on the >> vendor to rename the product when the internals change, so we would >> need a separate namespace anyway). > > > I can see that the vendor might change the internals without changing the > product name. That kind of thing happens too frequently across all kinds of > products. So, there are certainly disadvantages using consumer marketing > names here. > > Presumably though the name "big" would no longer apply to any modified HW? > Hence, I can't understand the need to say "nyan-big" rather than just "big". > Is "nyan-" really needed to fully qualify the name? Also, the board isn't a > Nyan, albeit the design may have been strongly derived from the reference > board named Nyan. it's more about partitioning the namespace and showing similarities (nyan-big and nyan-foo might be able to share a common dtsi for most of the platform, for example). See https://chromium.googlesource.com/chromiumos/third_party/kernel-next/+/chromeos-3.10/arch/arm/boot/dts/ for how it's done in the product tree (some of those bindings are of course divergent from upstream, so it's more about the file structure in this case). It's a model that's working pretty well for us w.r.t sharing/inheriting/expanding dts contents. If you have a better idea we'd be willing to consider it, of course. -Olof ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <CAOesGMgeLbuURwA1VVxkLp=vH9PB_VdUHFJthH=ae-_ZDVYyAA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <CAOesGMgeLbuURwA1VVxkLp=vH9PB_VdUHFJthH=ae-_ZDVYyAA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-08-13 20:17 ` Stephen Warren 0 siblings, 0 replies; 28+ messages in thread From: Stephen Warren @ 2014-08-13 20:17 UTC (permalink / raw) To: Olof Johansson Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 08/13/2014 11:37 AM, Olof Johansson wrote: > On Wed, Aug 13, 2014 at 10:31 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: >> On 08/13/2014 11:23 AM, Olof Johansson wrote: >>> >>> On Wed, Aug 13, 2014 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> >>> wrote: >>>> >>>> On 08/12/2014 07:56 PM, Dylan Reid wrote: >>>>> >>>>> >>>>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>>>> processor and is similar to the Venice2 reference platform. >>>>> >>>>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>>>> and work on the 1366x768 models. I haven't tried on the HD systems >>>>> yet. >>>>> >>>>> WiFi does not yet work, it needs at least some PMIC changes to enable >>>>> the 32k clock. >>>>> >>>>> The elan trackpad is not yet functional but hopefully will be soon as >>>>> there are patches under review. >>>>> >>>>> There is also an issue on reboot because the TPM isn't reset. It will >>>>> cause the stock firmware to enter recovery mode. This can be worked >>>>> around by an EC-reset, press refresh and power at the same time. >>>> >>>> >>>> >>>>> diff --git a/arch/arm/boot/dts/tegra124-big.dts >>>>> b/arch/arm/boot/dts/tegra124-big.dts >>>> >>>> >>>> >>>> I think we need to include the SKU name in the filename and compatible >>>> value >>>> below, or at least plan out that for other SKUs, we'll add the SKU name >>>> on. >>>> >>>> >>>>> +/ { >>>>> + model = "Google Big"; >>>>> + compatible = "google,nyan-big", "nvidia,tegra124"; >>>> >>>> >>>> >>>> I think it'd be more user-friendly if the filename and compatible value >>>> more >>>> obviously tied to the end-user-visible product name. >>> >>> >>> We didn't prefix the reference platform on the very first one we >>> shipped (snow), but for the peach platforms we used peach-pit and >>> peach-pi. Those had different SoCs inside (albeit very similar ones), >>> so there was a reason for separate DTS files. >>> >>> Here, we should probably prefix with nyan (so tegra124-nyan-big.dts). >>> Users have shown themselves to be quite happy to use the internal >>> names, they also tend to be less confusing (since we can't rely on the >>> vendor to rename the product when the internals change, so we would >>> need a separate namespace anyway). >> >> >> I can see that the vendor might change the internals without changing the >> product name. That kind of thing happens too frequently across all kinds of >> products. So, there are certainly disadvantages using consumer marketing >> names here. >> >> Presumably though the name "big" would no longer apply to any modified HW? >> Hence, I can't understand the need to say "nyan-big" rather than just "big". >> Is "nyan-" really needed to fully qualify the name? Also, the board isn't a >> Nyan, albeit the design may have been strongly derived from the reference >> board named Nyan. > > it's more about partitioning the namespace and showing similarities > (nyan-big and nyan-foo might be able to share a common dtsi for most > of the platform, for example). I don't think the files need to have a common prefix to include common content. In other words, assuming the naming made sense, the following would be fine if it represented reality: tegra124-nyan.dtsi represents common parts of a reference design tegra124-foo.dts includes tegra124-foo.dts tegra124-bar.dts includes tegra124-foo.dts > See https://chromium.googlesource.com/chromiumos/third_party/kernel-next/+/chromeos-3.10/arch/arm/boot/dts/ > for how it's done in the product tree (some of those bindings are of > course divergent from upstream, so it's more about the file structure > in this case). I've actually disliked the fact that the Venice2 board was represented as tegra124-nyan-rev0.dts rather than tegra124-venice2.dts there... ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <53EB9BF0.9010002-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2014-08-13 17:23 ` Olof Johansson @ 2014-08-13 19:07 ` Dylan Reid 2014-08-13 19:56 ` Stephen Warren 1 sibling, 1 reply; 28+ messages in thread From: Dylan Reid @ 2014-08-13 19:07 UTC (permalink / raw) To: Stephen Warren Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org On Wed, Aug 13, 2014 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 08/12/2014 07:56 PM, Dylan Reid wrote: >> >> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> processor and is similar to the Venice2 reference platform. >> >> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> and work on the 1366x768 models. I haven't tried on the HD systems >> yet. >> >> WiFi does not yet work, it needs at least some PMIC changes to enable >> the 32k clock. >> >> The elan trackpad is not yet functional but hopefully will be soon as >> there are patches under review. >> >> There is also an issue on reboot because the TPM isn't reset. It will >> cause the stock firmware to enter recovery mode. This can be worked >> around by an EC-reset, press refresh and power at the same time. > > >> diff --git a/arch/arm/boot/dts/tegra124-big.dts >> b/arch/arm/boot/dts/tegra124-big.dts > > > I think we need to include the SKU name in the filename and compatible value > below, or at least plan out that for other SKUs, we'll add the SKU name on. > > >> +/ { >> + model = "Google Big"; >> + compatible = "google,nyan-big", "nvidia,tegra124"; > > > I think it'd be more user-friendly if the filename and compatible value more > obviously tied to the end-user-visible product name. I'll change the model to "Acer Chromebook 13" If we need a separate DT for the FullHD skew, then can we add a file 'tegra124-nyan-big-full-hd.dtsi'? We may also add 'tegra124-nyan-big-full-hd-touch.dtsi' as well. They would just override the necessary things from this file. > > >> + gpio-keys { >> + compatible = "gpio-keys"; >> + >> + lid { >> + label = "Lid"; >> + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; >> + linux,input-type = <5>; >> + linux,code = <0>; > > > Aren't there #defines for the 5 and 0 there? yes for code, apparently not for input-type. I think 5 means EV_SW, maybe that should get added to include/dt-bindings/input somewhere? > > >> + sound { >> + compatible = "nvidia,tegra-audio-max98090-venice2", >> + "nvidia,tegra-audio-max98090"; >> + nvidia,model = "NVIDIA Tegra Venice2"; > > > Those strings should all use the same board name as the filename, compatible > value, and model of the root node. Based on the content in your patch, I > would expect: > > compatible = "nvidia,tegra-audio-max98090-big", > "nvidia,tegra-audio-max98090"; > nvidia,model = "Google Big"; Changed model to Acer Chromebook 13 and the compativle string to 'nyan-big'. > > In particular, nvidia,model is used to index into /var/lib/alsa/asound.state > by name, so it needs to be unique for each board. > > >> + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7) >> + GPIO_ACTIVE_HIGH>; > > > That property doesn't (yet) exist in the binding/code upstream. It could > obviously be added. I will remove it from this patch, and get it added to the driver first. Thanks for reviewing! ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree 2014-08-13 19:07 ` Dylan Reid @ 2014-08-13 19:56 ` Stephen Warren [not found] ` <53EBC2EC.1010300-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 0 siblings, 1 reply; 28+ messages in thread From: Stephen Warren @ 2014-08-13 19:56 UTC (permalink / raw) To: Dylan Reid Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org On 08/13/2014 01:07 PM, Dylan Reid wrote: > On Wed, Aug 13, 2014 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: >> On 08/12/2014 07:56 PM, Dylan Reid wrote: >>> >>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>> processor and is similar to the Venice2 reference platform. >>> >>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>> and work on the 1366x768 models. I haven't tried on the HD systems >>> yet. >>> >>> WiFi does not yet work, it needs at least some PMIC changes to enable >>> the 32k clock. >>> >>> The elan trackpad is not yet functional but hopefully will be soon as >>> there are patches under review. >>> >>> There is also an issue on reboot because the TPM isn't reset. It will >>> cause the stock firmware to enter recovery mode. This can be worked >>> around by an EC-reset, press refresh and power at the same time. >> >> >>> diff --git a/arch/arm/boot/dts/tegra124-big.dts >>> b/arch/arm/boot/dts/tegra124-big.dts >> >> >> I think we need to include the SKU name in the filename and compatible value >> below, or at least plan out that for other SKUs, we'll add the SKU name on. >> >> >>> +/ { >>> + model = "Google Big"; >>> + compatible = "google,nyan-big", "nvidia,tegra124"; >> >> >> I think it'd be more user-friendly if the filename and compatible value more >> obviously tied to the end-user-visible product name. > > I'll change the model to "Acer Chromebook 13" Would mentioning "CB5" in the model be a good idea; that's what it's sold as. > If we need a separate DT for the FullHD skew, then can we add a file > 'tegra124-nyan-big-full-hd.dtsi'? We may also add > 'tegra124-nyan-big-full-hd-touch.dtsi' as well. They would just > override the necessary things from this file. *.dts rather than *.dtsi I suspect? Yes, having a common include file and separate top-level files sounds like a good idea. >>> + gpio-keys { >>> + compatible = "gpio-keys"; >>> + >>> + lid { >>> + label = "Lid"; >>> + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; >>> + linux,input-type = <5>; >>> + linux,code = <0>; >> >> >> Aren't there #defines for the 5 and 0 there? > > yes for code, apparently not for input-type. I think 5 means EV_SW, > maybe that should get added to include/dt-bindings/input somewhere? Yes, that sounds like a good idea. ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <53EBC2EC.1010300-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <53EBC2EC.1010300-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2014-08-14 8:40 ` Dylan Reid 0 siblings, 0 replies; 28+ messages in thread From: Dylan Reid @ 2014-08-14 8:40 UTC (permalink / raw) To: Stephen Warren Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org On Wed, Aug 13, 2014 at 12:56 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 08/13/2014 01:07 PM, Dylan Reid wrote: >> >> On Wed, Aug 13, 2014 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> >> wrote: >>> >>> On 08/12/2014 07:56 PM, Dylan Reid wrote: >>>> >>>> >>>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>>> processor and is similar to the Venice2 reference platform. >>>> >>>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>>> and work on the 1366x768 models. I haven't tried on the HD systems >>>> yet. >>>> >>>> WiFi does not yet work, it needs at least some PMIC changes to enable >>>> the 32k clock. >>>> >>>> The elan trackpad is not yet functional but hopefully will be soon as >>>> there are patches under review. >>>> >>>> There is also an issue on reboot because the TPM isn't reset. It will >>>> cause the stock firmware to enter recovery mode. This can be worked >>>> around by an EC-reset, press refresh and power at the same time. >>> >>> >>> >>>> diff --git a/arch/arm/boot/dts/tegra124-big.dts >>>> b/arch/arm/boot/dts/tegra124-big.dts >>> >>> >>> >>> I think we need to include the SKU name in the filename and compatible >>> value >>> below, or at least plan out that for other SKUs, we'll add the SKU name >>> on. >>> >>> >>>> +/ { >>>> + model = "Google Big"; >>>> + compatible = "google,nyan-big", "nvidia,tegra124"; >>> >>> >>> >>> I think it'd be more user-friendly if the filename and compatible value >>> more >>> obviously tied to the end-user-visible product name. >> >> >> I'll change the model to "Acer Chromebook 13" > > > Would mentioning "CB5" in the model be a good idea; that's what it's sold > as. I am OK with either, most of the press has referred to "Acer Chromebook 13" although the CB5-311 model number has showed up a few times too. > > >> If we need a separate DT for the FullHD skew, then can we add a file >> 'tegra124-nyan-big-full-hd.dtsi'? We may also add >> 'tegra124-nyan-big-full-hd-touch.dtsi' as well. They would just >> override the necessary things from this file. > > > *.dts rather than *.dtsi I suspect? Yes, having a common include file and > separate top-level files sounds like a good idea. > > >>>> + gpio-keys { >>>> + compatible = "gpio-keys"; >>>> + >>>> + lid { >>>> + label = "Lid"; >>>> + gpios = <&gpio TEGRA_GPIO(R, 4) >>>> GPIO_ACTIVE_LOW>; >>>> + linux,input-type = <5>; >>>> + linux,code = <0>; >>> >>> >>> >>> Aren't there #defines for the 5 and 0 there? >> >> >> yes for code, apparently not for input-type. I think 5 means EV_SW, >> maybe that should get added to include/dt-bindings/input somewhere? > > > Yes, that sounds like a good idea. > ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <1407894967-18300-1-git-send-email-dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> 2014-08-13 8:53 ` Thierry Reding 2014-08-13 17:10 ` Stephen Warren @ 2015-01-13 17:49 ` Tomeu Vizoso [not found] ` <CAAObsKCbJLwEHeiv3DbCwsiVSZ0VDGzU84+ipPKJQZajx+KiuQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-01-19 9:01 ` Tomeu Vizoso 3 siblings, 1 reply; 28+ messages in thread From: Tomeu Vizoso @ 2015-01-13 17:49 UTC (permalink / raw) To: Dylan Reid Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On 13 August 2014 at 03:56, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: > The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 > processor and is similar to the Venice2 reference platform. > > The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested > and work on the 1366x768 models. I haven't tried on the HD systems > yet. Hi Dylan, do you have any notes on how you tested audio? I have been fiddling a bit with amixer but haven't been able to get any sound from the speakers nor the headphones. Thanks, Tomeu > WiFi does not yet work, it needs at least some PMIC changes to enable > the 32k clock. > > The elan trackpad is not yet functional but hopefully will be soon as > there are patches under review. > > There is also an issue on reboot because the TPM isn't reset. It will > cause the stock firmware to enter recovery mode. This can be worked > around by an EC-reset, press refresh and power at the same time. > > Signed-off-by: Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > --- > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/tegra124-big.dts | 1137 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 1138 insertions(+) > create mode 100644 arch/arm/boot/dts/tegra124-big.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index acb6b42..b0ab6a6 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -439,6 +439,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ > tegra114-dalmore.dtb \ > tegra114-roth.dtb \ > tegra114-tn7.dtb \ > + tegra124-big.dtb \ > tegra124-jetson-tk1.dtb \ > tegra124-venice2.dtb > dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb > diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts > new file mode 100644 > index 0000000..aa0cd9f > --- /dev/null > +++ b/arch/arm/boot/dts/tegra124-big.dts > @@ -0,0 +1,1137 @@ > +/dts-v1/; > + > +#include <dt-bindings/input/input.h> > +#include "tegra124.dtsi" > + > +/ { > + model = "Google Big"; > + compatible = "google,nyan-big", "nvidia,tegra124"; > + > + aliases { > + rtc0 = "/i2c@0,7000d000/pmic@40"; > + rtc1 = "/rtc@0,7000e000"; > + }; > + > + memory { > + reg = <0x0 0x80000000 0x0 0x80000000>; > + }; > + > + host1x@0,50000000 { > + hdmi@0,54280000 { > + status = "okay"; > + > + vdd-supply = <&vdd_3v3_hdmi>; > + pll-supply = <&vdd_hdmi_pll>; > + hdmi-supply = <&vdd_5v0_hdmi>; > + > + nvidia,ddc-i2c-bus = <&hdmi_ddc>; > + nvidia,hpd-gpio = > + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; > + }; > + > + sor@0,54540000 { > + status = "okay"; > + > + nvidia,dpaux = <&dpaux>; > + nvidia,panel = <&panel>; > + }; > + > + dpaux: dpaux@0,545c0000 { > + vdd-supply = <&vdd_3v3_panel>; > + status = "okay"; > + }; > + }; > + > + pinmux: pinmux@0,70000868 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinmux_default>; > + > + pinmux_default: common { > + dap_mclk1_pw4 { > + nvidia,pins = "dap_mclk1_pw4"; > + nvidia,function = "extperiph1"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + dap2_din_pa4 { > + nvidia,pins = "dap2_din_pa4"; > + nvidia,function = "i2s1"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + dap2_dout_pa5 { > + nvidia,pins = "dap2_dout_pa5", > + "dap2_fs_pa2", > + "dap2_sclk_pa3"; > + nvidia,function = "i2s1"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + dvfs_pwm_px0 { > + nvidia,pins = "dvfs_pwm_px0", > + "dvfs_clk_px2"; > + nvidia,function = "cldvfs"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + ulpi_clk_py0 { > + nvidia,pins = "ulpi_clk_py0", > + "ulpi_nxt_py2", > + "ulpi_stp_py3"; > + nvidia,function = "spi1"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + ulpi_dir_py1 { > + nvidia,pins = "ulpi_dir_py1"; > + nvidia,function = "spi1"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + cam_i2c_scl_pbb1 { > + nvidia,pins = "cam_i2c_scl_pbb1", > + "cam_i2c_sda_pbb2"; > + nvidia,function = "i2c3"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,lock = <TEGRA_PIN_DISABLE>; > + nvidia,open-drain = <TEGRA_PIN_ENABLE>; > + }; > + gen2_i2c_scl_pt5 { > + nvidia,pins = "gen2_i2c_scl_pt5", > + "gen2_i2c_sda_pt6"; > + nvidia,function = "i2c2"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,lock = <TEGRA_PIN_DISABLE>; > + nvidia,open-drain = <TEGRA_PIN_ENABLE>; > + }; > + pg4 { > + nvidia,pins = "pg4", > + "pg5", > + "pg6", > + "pi3"; > + nvidia,function = "spi4"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + pg7 { > + nvidia,pins = "pg7"; > + nvidia,function = "spi4"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + ph1 { > + nvidia,pins = "ph1"; > + nvidia,function = "pwm1"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + pk0 { > + nvidia,pins = "pk0", > + "kb_row15_ps7", > + "clk_32k_out_pa0"; > + nvidia,function = "soc"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + sdmmc1_clk_pz0 { > + nvidia,pins = "sdmmc1_clk_pz0"; > + nvidia,function = "sdmmc1"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + sdmmc1_cmd_pz1 { > + nvidia,pins = "sdmmc1_cmd_pz1", > + "sdmmc1_dat0_py7", > + "sdmmc1_dat1_py6", > + "sdmmc1_dat2_py5", > + "sdmmc1_dat3_py4"; > + nvidia,function = "sdmmc1"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + sdmmc3_clk_pa6 { > + nvidia,pins = "sdmmc3_clk_pa6"; > + nvidia,function = "sdmmc3"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + sdmmc3_cmd_pa7 { > + nvidia,pins = "sdmmc3_cmd_pa7", > + "sdmmc3_dat0_pb7", > + "sdmmc3_dat1_pb6", > + "sdmmc3_dat2_pb5", > + "sdmmc3_dat3_pb4", > + "kb_col4_pq4", > + "sdmmc3_clk_lb_out_pee4", > + "sdmmc3_clk_lb_in_pee5", > + "sdmmc3_cd_n_pv2"; > + nvidia,function = "sdmmc3"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + sdmmc4_clk_pcc4 { > + nvidia,pins = "sdmmc4_clk_pcc4"; > + nvidia,function = "sdmmc4"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + sdmmc4_cmd_pt7 { > + nvidia,pins = "sdmmc4_cmd_pt7", > + "sdmmc4_dat0_paa0", > + "sdmmc4_dat1_paa1", > + "sdmmc4_dat2_paa2", > + "sdmmc4_dat3_paa3", > + "sdmmc4_dat4_paa4", > + "sdmmc4_dat5_paa5", > + "sdmmc4_dat6_paa6", > + "sdmmc4_dat7_paa7"; > + nvidia,function = "sdmmc4"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + pwr_i2c_scl_pz6 { > + nvidia,pins = "pwr_i2c_scl_pz6", > + "pwr_i2c_sda_pz7"; > + nvidia,function = "i2cpwr"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,lock = <TEGRA_PIN_DISABLE>; > + nvidia,open-drain = <TEGRA_PIN_ENABLE>; > + }; > + jtag_rtck { > + nvidia,pins = "jtag_rtck"; > + nvidia,function = "rtck"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + clk_32k_in { > + nvidia,pins = "clk_32k_in"; > + nvidia,function = "clk"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + core_pwr_req { > + nvidia,pins = "core_pwr_req"; > + nvidia,function = "pwron"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + cpu_pwr_req { > + nvidia,pins = "cpu_pwr_req"; > + nvidia,function = "cpu"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + pwr_int_n { > + nvidia,pins = "pwr_int_n"; > + nvidia,function = "pmi"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + reset_out_n { > + nvidia,pins = "reset_out_n"; > + nvidia,function = "reset_out_n"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + clk3_out_pee0 { > + nvidia,pins = "clk3_out_pee0"; > + nvidia,function = "extperiph3"; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + gen1_i2c_sda_pc5 { > + nvidia,pins = "gen1_i2c_sda_pc5", > + "gen1_i2c_scl_pc4"; > + nvidia,function = "i2c1"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,lock = <TEGRA_PIN_DISABLE>; > + nvidia,open-drain = <TEGRA_PIN_ENABLE>; > + }; > + hdmi_cec_pee3 { > + nvidia,pins = "hdmi_cec_pee3"; > + nvidia,function = "cec"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,lock = <TEGRA_PIN_DISABLE>; > + nvidia,open-drain = <TEGRA_PIN_DISABLE>; > + }; > + hdmi_int_pn7 { > + nvidia,pins = "hdmi_int_pn7"; > + nvidia,function = "rsvd1"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + }; > + ddc_scl_pv4 { > + nvidia,pins = "ddc_scl_pv4", > + "ddc_sda_pv5"; > + nvidia,function = "i2c4"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,lock = <TEGRA_PIN_DISABLE>; > + nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; > + }; > + kb_row10_ps2 { > + nvidia,pins = "kb_row10_ps2"; > + nvidia,function = "uarta"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + kb_row9_ps1 { > + nvidia,pins = "kb_row9_ps1"; > + nvidia,function = "uarta"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + usb_vbus_en0_pn4 { > + nvidia,pins = "usb_vbus_en0_pn4", > + "usb_vbus_en1_pn5"; > + nvidia,function = "usb"; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,lock = <TEGRA_PIN_DISABLE>; > + nvidia,open-drain = <TEGRA_PIN_ENABLE>; > + }; > + drive_sdio1 { > + nvidia,pins = "drive_sdio1"; > + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; > + nvidia,schmitt = <TEGRA_PIN_DISABLE>; > + nvidia,pull-down-strength = <36>; > + nvidia,pull-up-strength = <20>; > + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; > + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; > + }; > + drive_sdio3 { > + nvidia,pins = "drive_sdio3"; > + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; > + nvidia,schmitt = <TEGRA_PIN_DISABLE>; > + nvidia,pull-down-strength = <22>; > + nvidia,pull-up-strength = <36>; > + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; > + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; > + }; > + drive_gma { > + nvidia,pins = "drive_gma"; > + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; > + nvidia,schmitt = <TEGRA_PIN_DISABLE>; > + nvidia,pull-down-strength = <2>; > + nvidia,pull-up-strength = <1>; > + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; > + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; > + nvidia,drive-type = <1>; > + }; > + codec_irq_l { > + nvidia,pins = "ph4"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + lcd_bl_en { > + nvidia,pins = "ph2"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + touch_irq_l { > + nvidia,pins = "gpio_w3_aud_pw3"; > + nvidia,function = "spi6"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + tpm_davint_l { > + nvidia,pins = "ph6"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + ts_irq_l { > + nvidia,pins = "pk2"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + ts_reset_l { > + nvidia,pins = "pk4"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + ts_shdn_l { > + nvidia,pins = "pk1"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + ph7 { > + nvidia,pins = "ph7"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + kb_col0_ap { > + nvidia,pins = "kb_col0_pq0"; > + nvidia,function = "rsvd4"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + lid_open { > + nvidia,pins = "kb_row4_pr4"; > + nvidia,function = "rsvd3"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + en_vdd_sd { > + nvidia,pins = "kb_row0_pr0"; > + nvidia,function = "rsvd4"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + ac_ok { > + nvidia,pins = "pj0"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + sensor_irq_l { > + nvidia,pins = "pi6"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + wifi_en { > + nvidia,pins = "gpio_x7_aud_px7"; > + nvidia,function = "rsvd4"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + en_vdd_bl { > + nvidia,pins = "dap3_dout_pp2"; > + nvidia,function = "i2s2"; > + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + en_vdd_hdmi { > + nvidia,pins = "spdif_in_pk6"; > + nvidia,function = "spdif"; > + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + soc_warm_reset_l { > + nvidia,pins = "pi5"; > + nvidia,function = "gmi"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + }; > + hp_det_l { > + nvidia,pins = "pi7"; > + nvidia,function = "rsvd1"; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + mic_det_l { > + nvidia,pins = "kb_row7_pr7"; > + nvidia,function = "rsvd2"; > + nvidia,pull = <TEGRA_PIN_PULL_UP>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + }; > + }; > + }; > + > + serial@0,70006000 { > + status = "okay"; > + }; > + > + pwm: pwm@0,7000a000 { > + status = "okay"; > + }; > + > + i2c@0,7000c000 { > + status = "okay"; > + clock-frequency = <100000>; > + > + acodec: audio-codec@10 { > + compatible = "maxim,max98090"; > + reg = <0x10>; > + interrupt-parent = <&gpio>; > + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; > + }; > + > + temperature-sensor@4c { > + compatible = "ti,tmp451"; > + reg = <0x4c>; > + interrupt-parent = <&gpio>; > + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; > + > + #thermal-sensor-cells = <1>; > + }; > + }; > + > + i2c@0,7000c400 { > + status = "okay"; > + clock-frequency = <100000>; > + }; > + > + i2c@0,7000c500 { > + status = "okay"; > + clock-frequency = <400000>; > + > + tpm@20 { > + compatible = "infineon,slb9645tt"; > + reg = <0x20>; > + }; > + }; > + > + hdmi_ddc: i2c@0,7000c700 { > + status = "okay"; > + clock-frequency = <100000>; > + }; > + > + i2c@0,7000d000 { > + status = "okay"; > + clock-frequency = <400000>; > + > + pmic: pmic@40 { > + compatible = "ams,as3722"; > + reg = <0x40>; > + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; > + > + ams,system-power-controller; > + > + #interrupt-cells = <2>; > + interrupt-controller; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&as3722_default>; > + > + as3722_default: pinmux { > + gpio0 { > + pins = "gpio0"; > + function = "gpio"; > + bias-pull-down; > + }; > + > + gpio1 { > + pins = "gpio1"; > + function = "gpio"; > + bias-pull-up; > + }; > + > + gpio2_4_7 { > + pins = "gpio2", "gpio4", "gpio7"; > + function = "gpio"; > + bias-pull-up; > + }; > + > + gpio3_6 { > + pins = "gpio3", "gpio6"; > + bias-high-impedance; > + }; > + > + gpio5 { > + pins = "gpio5"; > + function = "clk32k-out"; > + bias-pull-down; > + }; > + }; > + > + regulators { > + vsup-sd2-supply = <&vdd_5v0_sys>; > + vsup-sd3-supply = <&vdd_5v0_sys>; > + vsup-sd4-supply = <&vdd_5v0_sys>; > + vsup-sd5-supply = <&vdd_5v0_sys>; > + vin-ldo0-supply = <&vdd_1v35_lp0>; > + vin-ldo1-6-supply = <&vdd_3v3_run>; > + vin-ldo2-5-7-supply = <&vddio_1v8>; > + vin-ldo3-4-supply = <&vdd_3v3_sys>; > + vin-ldo9-10-supply = <&vdd_5v0_sys>; > + vin-ldo11-supply = <&vdd_3v3_run>; > + > + sd0 { > + regulator-name = "+VDD_CPU_AP"; > + regulator-min-microvolt = <700000>; > + regulator-max-microvolt = <1350000>; > + regulator-min-microamp = <3500000>; > + regulator-max-microamp = <3500000>; > + regulator-always-on; > + regulator-boot-on; > + ams,ext-control = <2>; > + }; > + > + sd1 { > + regulator-name = "+VDD_CORE"; > + regulator-min-microvolt = <700000>; > + regulator-max-microvolt = <1350000>; > + regulator-min-microamp = <2500000>; > + regulator-max-microamp = <4000000>; > + regulator-always-on; > + regulator-boot-on; > + ams,ext-control = <1>; > + }; > + > + vdd_1v35_lp0: sd2 { > + regulator-name = "+1.35V_LP0(sd2)"; > + regulator-min-microvolt = <1350000>; > + regulator-max-microvolt = <1350000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + sd3 { > + regulator-name = "+1.35V_LP0(sd3)"; > + regulator-min-microvolt = <1350000>; > + regulator-max-microvolt = <1350000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + vdd_1v05_run: sd4 { > + regulator-name = "+1.05V_RUN"; > + regulator-min-microvolt = <1050000>; > + regulator-max-microvolt = <1050000>; > + }; > + > + vddio_1v8: sd5 { > + regulator-name = "+1.8V_VDDIO"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + sd6 { > + regulator-name = "+VDD_GPU_AP"; > + regulator-min-microvolt = <650000>; > + regulator-max-microvolt = <1200000>; > + regulator-min-microamp = <3500000>; > + regulator-max-microamp = <3500000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo0 { > + regulator-name = "+1.05V_RUN_AVDD"; > + regulator-min-microvolt = <1050000>; > + regulator-max-microvolt = <1050000>; > + regulator-boot-on; > + regulator-always-on; > + ams,ext-control = <1>; > + }; > + > + ldo1 { > + regulator-name = "+1.8V_RUN_CAM"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + ldo2 { > + regulator-name = "+1.2V_GEN_AVDD"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo3 { > + regulator-name = "+1.00V_LP0_VDD_RTC"; > + regulator-min-microvolt = <1000000>; > + regulator-max-microvolt = <1000000>; > + regulator-boot-on; > + regulator-always-on; > + ams,enable-tracking; > + }; > + > + vdd_run_cam: ldo4 { > + regulator-name = "+3.3V_RUN_CAM"; > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <2800000>; > + }; > + > + ldo5 { > + regulator-name = "+1.2V_RUN_CAM_FRONT"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + }; > + > + vddio_sdmmc3: ldo6 { > + regulator-name = "+VDDIO_SDMMC3"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + }; > + > + ldo7 { > + regulator-name = "+1.05V_RUN_CAM_REAR"; > + regulator-min-microvolt = <1050000>; > + regulator-max-microvolt = <1050000>; > + }; > + > + ldo9 { > + regulator-name = "+2.8V_RUN_TOUCH"; > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <2800000>; > + }; > + > + ldo10 { > + regulator-name = "+2.8V_RUN_CAM_AF"; > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <2800000>; > + }; > + > + ldo11 { > + regulator-name = "+1.8V_RUN_VPP_FUSE"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + }; > + }; > + }; > + > + spi@0,7000d400 { > + status = "okay"; > + > + cros_ec: cros-ec@0 { > + compatible = "google,cros-ec-spi"; > + spi-max-frequency = <3000000>; > + interrupt-parent = <&gpio>; > + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; > + reg = <0>; > + > + google,cros-ec-spi-msg-delay = <2000>; > + > + i2c-tunnel { > + compatible = "google,cros-ec-i2c-tunnel"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + google,remote-bus = <0>; > + > + charger: bq24735@9 { > + compatible = "ti,bq24735"; > + reg = <0x9>; > + interrupt-parent = <&gpio>; > + interrupts = <TEGRA_GPIO(J, 0) > + GPIO_ACTIVE_HIGH>; > + ti,ac-detect-gpios = <&gpio > + TEGRA_GPIO(J, 0) > + GPIO_ACTIVE_HIGH>; > + }; > + > + battery: sbs-battery@b { > + compatible = "sbs,sbs-battery"; > + reg = <0xb>; > + sbs,i2c-retry-count = <2>; > + sbs,poll-retry-count = <10>; > + power-supplies = <&charger>; > + }; > + }; > + }; > + }; > + > + spi@0,7000da00 { > + status = "okay"; > + spi-max-frequency = <25000000>; > + spi-flash@0 { > + compatible = "winbond,w25q32dw"; > + reg = <0>; > + spi-max-frequency = <25000000>; > + }; > + }; > + > + pmc@0,7000e400 { > + nvidia,invert-interrupt; > + nvidia,suspend-mode = <0>; > + nvidia,cpu-pwr-good-time = <500>; > + nvidia,cpu-pwr-off-time = <300>; > + nvidia,core-pwr-good-time = <641 3845>; > + nvidia,core-pwr-off-time = <61036>; > + nvidia,core-power-req-active-high; > + nvidia,sys-clock-req-active-high; > + }; > + > + hda@0,70030000 { > + status = "okay"; > + }; > + > + sdhci@0,700b0000 { > + status = "okay"; > + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; > + bus-width = <4>; > + no-1-8-v; > + non-removable; > + }; > + > + sdhci@0,700b0400 { > + status = "okay"; > + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; > + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; > + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; > + bus-width = <4>; > + no-1-8-v; > + vqmmc-supply = <&vddio_sdmmc3>; > + }; > + > + sdhci@0,700b0600 { > + status = "okay"; > + bus-width = <8>; > + no-1-8-v; > + non-removable; > + }; > + > + ahub@0,70300000 { > + i2s@0,70301100 { > + status = "okay"; > + }; > + }; > + > + usb@0,7d000000 { > + status = "okay"; > + }; > + > + usb-phy@0,7d000000 { > + status = "okay"; > + vbus-supply = <&vdd_usb1_vbus>; > + }; > + > + usb@0,7d004000 { > + status = "okay"; > + }; > + > + usb-phy@0,7d004000 { > + status = "okay"; > + vbus-supply = <&vdd_run_cam>; > + }; > + > + usb@0,7d008000 { > + status = "okay"; > + }; > + > + usb-phy@0,7d008000 { > + status = "okay"; > + vbus-supply = <&vdd_usb3_vbus>; > + }; > + > + backlight: backlight { > + compatible = "pwm-backlight"; > + > + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; > + power-supply = <&vdd_led>; > + pwms = <&pwm 1 1000000>; > + > + default-brightness-level = <224>; > + brightness-levels = > + < 0 1 2 3 4 5 6 7 > + 8 9 10 11 12 13 14 15 > + 16 17 18 19 20 21 22 23 > + 24 25 26 27 28 29 30 31 > + 32 33 34 35 36 37 38 39 > + 40 41 42 43 44 45 46 47 > + 48 49 50 51 52 53 54 55 > + 56 57 58 59 60 61 62 63 > + 64 65 66 67 68 69 70 71 > + 72 73 74 75 76 77 78 79 > + 80 81 82 83 84 85 86 87 > + 88 89 90 91 92 93 94 95 > + 96 97 98 99 100 101 102 103 > + 104 105 106 107 108 109 110 111 > + 112 113 114 115 116 117 118 119 > + 120 121 122 123 124 125 126 127 > + 128 129 130 131 132 133 134 135 > + 136 137 138 139 140 141 142 143 > + 144 145 146 147 148 149 150 151 > + 152 153 154 155 156 157 158 159 > + 160 161 162 163 164 165 166 167 > + 168 169 170 171 172 173 174 175 > + 176 177 178 179 180 181 182 183 > + 184 185 186 187 188 189 190 191 > + 192 193 194 195 196 197 198 199 > + 200 201 202 203 204 205 206 207 > + 208 209 210 211 212 213 214 215 > + 216 217 218 219 220 221 222 223 > + 224 225 226 227 228 229 230 231 > + 232 233 234 235 236 237 238 239 > + 240 241 242 243 244 245 246 247 > + 248 249 250 251 252 253 254 255 > + 256>; > + }; > + > + clocks { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + clk32k_in: clock@0 { > + compatible = "fixed-clock"; > + reg = <0>; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + }; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + > + lid { > + label = "Lid"; > + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; > + linux,input-type = <5>; > + linux,code = <0>; > + debounce-interval = <1>; > + gpio-key,wakeup; > + }; > + > + power { > + label = "Power"; > + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; > + linux,code = <KEY_POWER>; > + debounce-interval = <30>; > + gpio-key,wakeup; > + }; > + }; > + > + panel: panel { > + compatible = "auo,b133xtn01", "simple-panel"; > + > + backlight = <&backlight>; > + ddc-i2c-bus = <&dpaux>; > + }; > + > + regulators { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + vdd_mux: regulator@0 { > + compatible = "regulator-fixed"; > + reg = <0>; > + regulator-name = "+VDD_MUX"; > + regulator-min-microvolt = <12000000>; > + regulator-max-microvolt = <12000000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + vdd_5v0_sys: regulator@1 { > + compatible = "regulator-fixed"; > + reg = <1>; > + regulator-name = "+5V_SYS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + regulator-boot-on; > + vin-supply = <&vdd_mux>; > + }; > + > + vdd_3v3_sys: regulator@2 { > + compatible = "regulator-fixed"; > + reg = <2>; > + regulator-name = "+3.3V_SYS"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + regulator-boot-on; > + vin-supply = <&vdd_mux>; > + }; > + > + vdd_3v3_run: regulator@3 { > + compatible = "regulator-fixed"; > + reg = <3>; > + regulator-name = "+3.3V_RUN"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + regulator-boot-on; > + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + vin-supply = <&vdd_3v3_sys>; > + }; > + > + vdd_3v3_hdmi: regulator@4 { > + compatible = "regulator-fixed"; > + reg = <4>; > + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + vin-supply = <&vdd_3v3_run>; > + }; > + > + vdd_led: regulator@5 { > + compatible = "regulator-fixed"; > + reg = <5>; > + regulator-name = "+VDD_LED"; > + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; > + enable-active-high; > + vin-supply = <&vdd_mux>; > + }; > + > + vdd_5v0_ts: regulator@6 { > + compatible = "regulator-fixed"; > + reg = <6>; > + regulator-name = "+5V_VDD_TS_SW"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-boot-on; > + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; > + enable-active-high; > + vin-supply = <&vdd_5v0_sys>; > + }; > + > + vdd_usb1_vbus: regulator@7 { > + compatible = "regulator-fixed"; > + reg = <7>; > + regulator-name = "+5V_USB_HS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; > + enable-active-high; > + gpio-open-drain; > + vin-supply = <&vdd_5v0_sys>; > + }; > + > + vdd_usb3_vbus: regulator@8 { > + compatible = "regulator-fixed"; > + reg = <8>; > + regulator-name = "+5V_USB_SS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; > + enable-active-high; > + gpio-open-drain; > + vin-supply = <&vdd_5v0_sys>; > + }; > + > + vdd_3v3_panel: regulator@9 { > + compatible = "regulator-fixed"; > + reg = <9>; > + regulator-name = "+3.3V_PANEL"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + vin-supply = <&vdd_3v3_run>; > + }; > + > + vdd_3v3_lp0: regulator@10 { > + compatible = "regulator-fixed"; > + reg = <10>; > + regulator-name = "+3.3V_LP0"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + /* > + * TODO: find a way to wire this up with the USB EHCI > + * controllers so that it can be enabled on demand. > + */ > + regulator-always-on; > + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + vin-supply = <&vdd_3v3_sys>; > + }; > + > + vdd_hdmi_pll: regulator@11 { > + compatible = "regulator-fixed"; > + reg = <11>; > + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; > + regulator-min-microvolt = <1050000>; > + regulator-max-microvolt = <1050000>; > + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; > + vin-supply = <&vdd_1v05_run>; > + }; > + > + vdd_5v0_hdmi: regulator@12 { > + compatible = "regulator-fixed"; > + reg = <12>; > + regulator-name = "+5V_HDMI_CON"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; > + enable-active-high; > + vin-supply = <&vdd_5v0_sys>; > + }; > + }; > + > + sound { > + compatible = "nvidia,tegra-audio-max98090-venice2", > + "nvidia,tegra-audio-max98090"; > + nvidia,model = "NVIDIA Tegra Venice2"; > + > + nvidia,audio-routing = > + "Headphones", "HPR", > + "Headphones", "HPL", > + "Speakers", "SPKR", > + "Speakers", "SPKL", > + "Mic Jack", "MICBIAS", > + "DMICL", "Int Mic", > + "DMICR", "Int Mic", > + "IN34", "Mic Jack"; > + > + nvidia,i2s-controller = <&tegra_i2s1>; > + nvidia,audio-codec = <&acodec>; > + > + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, > + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, > + <&tegra_car TEGRA124_CLK_EXTERN1>; > + clock-names = "pll_a", "pll_a_out0", "mclk"; > + > + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; > + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7) > + GPIO_ACTIVE_HIGH>; > + }; > +}; > + > +#include "cros-ec-keyboard.dtsi" > -- > 2.1.0.rc2.206.gedb03e5 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-tegra" in > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <CAAObsKCbJLwEHeiv3DbCwsiVSZ0VDGzU84+ipPKJQZajx+KiuQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <CAAObsKCbJLwEHeiv3DbCwsiVSZ0VDGzU84+ipPKJQZajx+KiuQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2015-01-14 0:32 ` Dylan Reid 2015-01-14 7:02 ` Tomeu Vizoso 0 siblings, 1 reply; 28+ messages in thread From: Dylan Reid @ 2015-01-14 0:32 UTC (permalink / raw) To: Tomeu Vizoso Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On Tue, Jan 13, 2015 at 9:49 AM, Tomeu Vizoso <tomeu-XCtybt49RKsYaV1qd6yewg@public.gmane.org> wrote: > On 13 August 2014 at 03:56, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: >> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> processor and is similar to the Venice2 reference platform. >> >> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> and work on the 1366x768 models. I haven't tried on the HD systems >> yet. > > Hi Dylan, > > do you have any notes on how you tested audio? I have been fiddling a > bit with amixer but haven't been able to get any sound from the > speakers nor the headphones. I don't have any notes, and it's been a while since I tried it. To the best of my knowledge, I loaded the UCM config from the ChromeOS tree manually with alsaucm, then enabled/disabled headphones from there. https://chromium.googlesource.com/chromiumos/third_party/adhd/+/master/ucm-config/nyan/NVIDIA%20Tegra%20Venice2/ The important stuff is all in the enable sequence of HiFi.conf Let me know if that helps. Does playback appear to be working, except you can't hear anything or does aplay fail? > > Thanks, > > Tomeu > >> WiFi does not yet work, it needs at least some PMIC changes to enable >> the 32k clock. >> >> The elan trackpad is not yet functional but hopefully will be soon as >> there are patches under review. >> >> There is also an issue on reboot because the TPM isn't reset. It will >> cause the stock firmware to enter recovery mode. This can be worked >> around by an EC-reset, press refresh and power at the same time. >> >> Signed-off-by: Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> >> --- >> arch/arm/boot/dts/Makefile | 1 + >> arch/arm/boot/dts/tegra124-big.dts | 1137 ++++++++++++++++++++++++++++++++++++ >> 2 files changed, 1138 insertions(+) >> create mode 100644 arch/arm/boot/dts/tegra124-big.dts >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index acb6b42..b0ab6a6 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -439,6 +439,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ >> tegra114-dalmore.dtb \ >> tegra114-roth.dtb \ >> tegra114-tn7.dtb \ >> + tegra124-big.dtb \ >> tegra124-jetson-tk1.dtb \ >> tegra124-venice2.dtb >> dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb >> diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts >> new file mode 100644 >> index 0000000..aa0cd9f >> --- /dev/null >> +++ b/arch/arm/boot/dts/tegra124-big.dts >> @@ -0,0 +1,1137 @@ >> +/dts-v1/; >> + >> +#include <dt-bindings/input/input.h> >> +#include "tegra124.dtsi" >> + >> +/ { >> + model = "Google Big"; >> + compatible = "google,nyan-big", "nvidia,tegra124"; >> + >> + aliases { >> + rtc0 = "/i2c@0,7000d000/pmic@40"; >> + rtc1 = "/rtc@0,7000e000"; >> + }; >> + >> + memory { >> + reg = <0x0 0x80000000 0x0 0x80000000>; >> + }; >> + >> + host1x@0,50000000 { >> + hdmi@0,54280000 { >> + status = "okay"; >> + >> + vdd-supply = <&vdd_3v3_hdmi>; >> + pll-supply = <&vdd_hdmi_pll>; >> + hdmi-supply = <&vdd_5v0_hdmi>; >> + >> + nvidia,ddc-i2c-bus = <&hdmi_ddc>; >> + nvidia,hpd-gpio = >> + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; >> + }; >> + >> + sor@0,54540000 { >> + status = "okay"; >> + >> + nvidia,dpaux = <&dpaux>; >> + nvidia,panel = <&panel>; >> + }; >> + >> + dpaux: dpaux@0,545c0000 { >> + vdd-supply = <&vdd_3v3_panel>; >> + status = "okay"; >> + }; >> + }; >> + >> + pinmux: pinmux@0,70000868 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinmux_default>; >> + >> + pinmux_default: common { >> + dap_mclk1_pw4 { >> + nvidia,pins = "dap_mclk1_pw4"; >> + nvidia,function = "extperiph1"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + dap2_din_pa4 { >> + nvidia,pins = "dap2_din_pa4"; >> + nvidia,function = "i2s1"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + dap2_dout_pa5 { >> + nvidia,pins = "dap2_dout_pa5", >> + "dap2_fs_pa2", >> + "dap2_sclk_pa3"; >> + nvidia,function = "i2s1"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + dvfs_pwm_px0 { >> + nvidia,pins = "dvfs_pwm_px0", >> + "dvfs_clk_px2"; >> + nvidia,function = "cldvfs"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + ulpi_clk_py0 { >> + nvidia,pins = "ulpi_clk_py0", >> + "ulpi_nxt_py2", >> + "ulpi_stp_py3"; >> + nvidia,function = "spi1"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + ulpi_dir_py1 { >> + nvidia,pins = "ulpi_dir_py1"; >> + nvidia,function = "spi1"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + cam_i2c_scl_pbb1 { >> + nvidia,pins = "cam_i2c_scl_pbb1", >> + "cam_i2c_sda_pbb2"; >> + nvidia,function = "i2c3"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,lock = <TEGRA_PIN_DISABLE>; >> + nvidia,open-drain = <TEGRA_PIN_ENABLE>; >> + }; >> + gen2_i2c_scl_pt5 { >> + nvidia,pins = "gen2_i2c_scl_pt5", >> + "gen2_i2c_sda_pt6"; >> + nvidia,function = "i2c2"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,lock = <TEGRA_PIN_DISABLE>; >> + nvidia,open-drain = <TEGRA_PIN_ENABLE>; >> + }; >> + pg4 { >> + nvidia,pins = "pg4", >> + "pg5", >> + "pg6", >> + "pi3"; >> + nvidia,function = "spi4"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + pg7 { >> + nvidia,pins = "pg7"; >> + nvidia,function = "spi4"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + ph1 { >> + nvidia,pins = "ph1"; >> + nvidia,function = "pwm1"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + pk0 { >> + nvidia,pins = "pk0", >> + "kb_row15_ps7", >> + "clk_32k_out_pa0"; >> + nvidia,function = "soc"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + sdmmc1_clk_pz0 { >> + nvidia,pins = "sdmmc1_clk_pz0"; >> + nvidia,function = "sdmmc1"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + sdmmc1_cmd_pz1 { >> + nvidia,pins = "sdmmc1_cmd_pz1", >> + "sdmmc1_dat0_py7", >> + "sdmmc1_dat1_py6", >> + "sdmmc1_dat2_py5", >> + "sdmmc1_dat3_py4"; >> + nvidia,function = "sdmmc1"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + sdmmc3_clk_pa6 { >> + nvidia,pins = "sdmmc3_clk_pa6"; >> + nvidia,function = "sdmmc3"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + sdmmc3_cmd_pa7 { >> + nvidia,pins = "sdmmc3_cmd_pa7", >> + "sdmmc3_dat0_pb7", >> + "sdmmc3_dat1_pb6", >> + "sdmmc3_dat2_pb5", >> + "sdmmc3_dat3_pb4", >> + "kb_col4_pq4", >> + "sdmmc3_clk_lb_out_pee4", >> + "sdmmc3_clk_lb_in_pee5", >> + "sdmmc3_cd_n_pv2"; >> + nvidia,function = "sdmmc3"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + sdmmc4_clk_pcc4 { >> + nvidia,pins = "sdmmc4_clk_pcc4"; >> + nvidia,function = "sdmmc4"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + sdmmc4_cmd_pt7 { >> + nvidia,pins = "sdmmc4_cmd_pt7", >> + "sdmmc4_dat0_paa0", >> + "sdmmc4_dat1_paa1", >> + "sdmmc4_dat2_paa2", >> + "sdmmc4_dat3_paa3", >> + "sdmmc4_dat4_paa4", >> + "sdmmc4_dat5_paa5", >> + "sdmmc4_dat6_paa6", >> + "sdmmc4_dat7_paa7"; >> + nvidia,function = "sdmmc4"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + pwr_i2c_scl_pz6 { >> + nvidia,pins = "pwr_i2c_scl_pz6", >> + "pwr_i2c_sda_pz7"; >> + nvidia,function = "i2cpwr"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,lock = <TEGRA_PIN_DISABLE>; >> + nvidia,open-drain = <TEGRA_PIN_ENABLE>; >> + }; >> + jtag_rtck { >> + nvidia,pins = "jtag_rtck"; >> + nvidia,function = "rtck"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + clk_32k_in { >> + nvidia,pins = "clk_32k_in"; >> + nvidia,function = "clk"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + core_pwr_req { >> + nvidia,pins = "core_pwr_req"; >> + nvidia,function = "pwron"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + cpu_pwr_req { >> + nvidia,pins = "cpu_pwr_req"; >> + nvidia,function = "cpu"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + pwr_int_n { >> + nvidia,pins = "pwr_int_n"; >> + nvidia,function = "pmi"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + reset_out_n { >> + nvidia,pins = "reset_out_n"; >> + nvidia,function = "reset_out_n"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + clk3_out_pee0 { >> + nvidia,pins = "clk3_out_pee0"; >> + nvidia,function = "extperiph3"; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + gen1_i2c_sda_pc5 { >> + nvidia,pins = "gen1_i2c_sda_pc5", >> + "gen1_i2c_scl_pc4"; >> + nvidia,function = "i2c1"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,lock = <TEGRA_PIN_DISABLE>; >> + nvidia,open-drain = <TEGRA_PIN_ENABLE>; >> + }; >> + hdmi_cec_pee3 { >> + nvidia,pins = "hdmi_cec_pee3"; >> + nvidia,function = "cec"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,lock = <TEGRA_PIN_DISABLE>; >> + nvidia,open-drain = <TEGRA_PIN_DISABLE>; >> + }; >> + hdmi_int_pn7 { >> + nvidia,pins = "hdmi_int_pn7"; >> + nvidia,function = "rsvd1"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + }; >> + ddc_scl_pv4 { >> + nvidia,pins = "ddc_scl_pv4", >> + "ddc_sda_pv5"; >> + nvidia,function = "i2c4"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,lock = <TEGRA_PIN_DISABLE>; >> + nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; >> + }; >> + kb_row10_ps2 { >> + nvidia,pins = "kb_row10_ps2"; >> + nvidia,function = "uarta"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + kb_row9_ps1 { >> + nvidia,pins = "kb_row9_ps1"; >> + nvidia,function = "uarta"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + usb_vbus_en0_pn4 { >> + nvidia,pins = "usb_vbus_en0_pn4", >> + "usb_vbus_en1_pn5"; >> + nvidia,function = "usb"; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,lock = <TEGRA_PIN_DISABLE>; >> + nvidia,open-drain = <TEGRA_PIN_ENABLE>; >> + }; >> + drive_sdio1 { >> + nvidia,pins = "drive_sdio1"; >> + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; >> + nvidia,schmitt = <TEGRA_PIN_DISABLE>; >> + nvidia,pull-down-strength = <36>; >> + nvidia,pull-up-strength = <20>; >> + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; >> + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; >> + }; >> + drive_sdio3 { >> + nvidia,pins = "drive_sdio3"; >> + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; >> + nvidia,schmitt = <TEGRA_PIN_DISABLE>; >> + nvidia,pull-down-strength = <22>; >> + nvidia,pull-up-strength = <36>; >> + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; >> + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; >> + }; >> + drive_gma { >> + nvidia,pins = "drive_gma"; >> + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; >> + nvidia,schmitt = <TEGRA_PIN_DISABLE>; >> + nvidia,pull-down-strength = <2>; >> + nvidia,pull-up-strength = <1>; >> + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; >> + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; >> + nvidia,drive-type = <1>; >> + }; >> + codec_irq_l { >> + nvidia,pins = "ph4"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + lcd_bl_en { >> + nvidia,pins = "ph2"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + touch_irq_l { >> + nvidia,pins = "gpio_w3_aud_pw3"; >> + nvidia,function = "spi6"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + tpm_davint_l { >> + nvidia,pins = "ph6"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + ts_irq_l { >> + nvidia,pins = "pk2"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + ts_reset_l { >> + nvidia,pins = "pk4"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + ts_shdn_l { >> + nvidia,pins = "pk1"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + ph7 { >> + nvidia,pins = "ph7"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + kb_col0_ap { >> + nvidia,pins = "kb_col0_pq0"; >> + nvidia,function = "rsvd4"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + lid_open { >> + nvidia,pins = "kb_row4_pr4"; >> + nvidia,function = "rsvd3"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + en_vdd_sd { >> + nvidia,pins = "kb_row0_pr0"; >> + nvidia,function = "rsvd4"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + ac_ok { >> + nvidia,pins = "pj0"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + sensor_irq_l { >> + nvidia,pins = "pi6"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + wifi_en { >> + nvidia,pins = "gpio_x7_aud_px7"; >> + nvidia,function = "rsvd4"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + en_vdd_bl { >> + nvidia,pins = "dap3_dout_pp2"; >> + nvidia,function = "i2s2"; >> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + en_vdd_hdmi { >> + nvidia,pins = "spdif_in_pk6"; >> + nvidia,function = "spdif"; >> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + soc_warm_reset_l { >> + nvidia,pins = "pi5"; >> + nvidia,function = "gmi"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_DISABLE>; >> + }; >> + hp_det_l { >> + nvidia,pins = "pi7"; >> + nvidia,function = "rsvd1"; >> + nvidia,pull = <TEGRA_PIN_PULL_NONE>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + mic_det_l { >> + nvidia,pins = "kb_row7_pr7"; >> + nvidia,function = "rsvd2"; >> + nvidia,pull = <TEGRA_PIN_PULL_UP>; >> + nvidia,tristate = <TEGRA_PIN_DISABLE>; >> + nvidia,enable-input = <TEGRA_PIN_ENABLE>; >> + }; >> + }; >> + }; >> + >> + serial@0,70006000 { >> + status = "okay"; >> + }; >> + >> + pwm: pwm@0,7000a000 { >> + status = "okay"; >> + }; >> + >> + i2c@0,7000c000 { >> + status = "okay"; >> + clock-frequency = <100000>; >> + >> + acodec: audio-codec@10 { >> + compatible = "maxim,max98090"; >> + reg = <0x10>; >> + interrupt-parent = <&gpio>; >> + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; >> + }; >> + >> + temperature-sensor@4c { >> + compatible = "ti,tmp451"; >> + reg = <0x4c>; >> + interrupt-parent = <&gpio>; >> + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; >> + >> + #thermal-sensor-cells = <1>; >> + }; >> + }; >> + >> + i2c@0,7000c400 { >> + status = "okay"; >> + clock-frequency = <100000>; >> + }; >> + >> + i2c@0,7000c500 { >> + status = "okay"; >> + clock-frequency = <400000>; >> + >> + tpm@20 { >> + compatible = "infineon,slb9645tt"; >> + reg = <0x20>; >> + }; >> + }; >> + >> + hdmi_ddc: i2c@0,7000c700 { >> + status = "okay"; >> + clock-frequency = <100000>; >> + }; >> + >> + i2c@0,7000d000 { >> + status = "okay"; >> + clock-frequency = <400000>; >> + >> + pmic: pmic@40 { >> + compatible = "ams,as3722"; >> + reg = <0x40>; >> + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; >> + >> + ams,system-power-controller; >> + >> + #interrupt-cells = <2>; >> + interrupt-controller; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + pinctrl-names = "default"; >> + pinctrl-0 = <&as3722_default>; >> + >> + as3722_default: pinmux { >> + gpio0 { >> + pins = "gpio0"; >> + function = "gpio"; >> + bias-pull-down; >> + }; >> + >> + gpio1 { >> + pins = "gpio1"; >> + function = "gpio"; >> + bias-pull-up; >> + }; >> + >> + gpio2_4_7 { >> + pins = "gpio2", "gpio4", "gpio7"; >> + function = "gpio"; >> + bias-pull-up; >> + }; >> + >> + gpio3_6 { >> + pins = "gpio3", "gpio6"; >> + bias-high-impedance; >> + }; >> + >> + gpio5 { >> + pins = "gpio5"; >> + function = "clk32k-out"; >> + bias-pull-down; >> + }; >> + }; >> + >> + regulators { >> + vsup-sd2-supply = <&vdd_5v0_sys>; >> + vsup-sd3-supply = <&vdd_5v0_sys>; >> + vsup-sd4-supply = <&vdd_5v0_sys>; >> + vsup-sd5-supply = <&vdd_5v0_sys>; >> + vin-ldo0-supply = <&vdd_1v35_lp0>; >> + vin-ldo1-6-supply = <&vdd_3v3_run>; >> + vin-ldo2-5-7-supply = <&vddio_1v8>; >> + vin-ldo3-4-supply = <&vdd_3v3_sys>; >> + vin-ldo9-10-supply = <&vdd_5v0_sys>; >> + vin-ldo11-supply = <&vdd_3v3_run>; >> + >> + sd0 { >> + regulator-name = "+VDD_CPU_AP"; >> + regulator-min-microvolt = <700000>; >> + regulator-max-microvolt = <1350000>; >> + regulator-min-microamp = <3500000>; >> + regulator-max-microamp = <3500000>; >> + regulator-always-on; >> + regulator-boot-on; >> + ams,ext-control = <2>; >> + }; >> + >> + sd1 { >> + regulator-name = "+VDD_CORE"; >> + regulator-min-microvolt = <700000>; >> + regulator-max-microvolt = <1350000>; >> + regulator-min-microamp = <2500000>; >> + regulator-max-microamp = <4000000>; >> + regulator-always-on; >> + regulator-boot-on; >> + ams,ext-control = <1>; >> + }; >> + >> + vdd_1v35_lp0: sd2 { >> + regulator-name = "+1.35V_LP0(sd2)"; >> + regulator-min-microvolt = <1350000>; >> + regulator-max-microvolt = <1350000>; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> + sd3 { >> + regulator-name = "+1.35V_LP0(sd3)"; >> + regulator-min-microvolt = <1350000>; >> + regulator-max-microvolt = <1350000>; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> + vdd_1v05_run: sd4 { >> + regulator-name = "+1.05V_RUN"; >> + regulator-min-microvolt = <1050000>; >> + regulator-max-microvolt = <1050000>; >> + }; >> + >> + vddio_1v8: sd5 { >> + regulator-name = "+1.8V_VDDIO"; >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + regulator-boot-on; >> + regulator-always-on; >> + }; >> + >> + sd6 { >> + regulator-name = "+VDD_GPU_AP"; >> + regulator-min-microvolt = <650000>; >> + regulator-max-microvolt = <1200000>; >> + regulator-min-microamp = <3500000>; >> + regulator-max-microamp = <3500000>; >> + regulator-boot-on; >> + regulator-always-on; >> + }; >> + >> + ldo0 { >> + regulator-name = "+1.05V_RUN_AVDD"; >> + regulator-min-microvolt = <1050000>; >> + regulator-max-microvolt = <1050000>; >> + regulator-boot-on; >> + regulator-always-on; >> + ams,ext-control = <1>; >> + }; >> + >> + ldo1 { >> + regulator-name = "+1.8V_RUN_CAM"; >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + }; >> + >> + ldo2 { >> + regulator-name = "+1.2V_GEN_AVDD"; >> + regulator-min-microvolt = <1200000>; >> + regulator-max-microvolt = <1200000>; >> + regulator-boot-on; >> + regulator-always-on; >> + }; >> + >> + ldo3 { >> + regulator-name = "+1.00V_LP0_VDD_RTC"; >> + regulator-min-microvolt = <1000000>; >> + regulator-max-microvolt = <1000000>; >> + regulator-boot-on; >> + regulator-always-on; >> + ams,enable-tracking; >> + }; >> + >> + vdd_run_cam: ldo4 { >> + regulator-name = "+3.3V_RUN_CAM"; >> + regulator-min-microvolt = <2800000>; >> + regulator-max-microvolt = <2800000>; >> + }; >> + >> + ldo5 { >> + regulator-name = "+1.2V_RUN_CAM_FRONT"; >> + regulator-min-microvolt = <1200000>; >> + regulator-max-microvolt = <1200000>; >> + }; >> + >> + vddio_sdmmc3: ldo6 { >> + regulator-name = "+VDDIO_SDMMC3"; >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <3300000>; >> + }; >> + >> + ldo7 { >> + regulator-name = "+1.05V_RUN_CAM_REAR"; >> + regulator-min-microvolt = <1050000>; >> + regulator-max-microvolt = <1050000>; >> + }; >> + >> + ldo9 { >> + regulator-name = "+2.8V_RUN_TOUCH"; >> + regulator-min-microvolt = <2800000>; >> + regulator-max-microvolt = <2800000>; >> + }; >> + >> + ldo10 { >> + regulator-name = "+2.8V_RUN_CAM_AF"; >> + regulator-min-microvolt = <2800000>; >> + regulator-max-microvolt = <2800000>; >> + }; >> + >> + ldo11 { >> + regulator-name = "+1.8V_RUN_VPP_FUSE"; >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + }; >> + }; >> + }; >> + }; >> + >> + spi@0,7000d400 { >> + status = "okay"; >> + >> + cros_ec: cros-ec@0 { >> + compatible = "google,cros-ec-spi"; >> + spi-max-frequency = <3000000>; >> + interrupt-parent = <&gpio>; >> + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; >> + reg = <0>; >> + >> + google,cros-ec-spi-msg-delay = <2000>; >> + >> + i2c-tunnel { >> + compatible = "google,cros-ec-i2c-tunnel"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + google,remote-bus = <0>; >> + >> + charger: bq24735@9 { >> + compatible = "ti,bq24735"; >> + reg = <0x9>; >> + interrupt-parent = <&gpio>; >> + interrupts = <TEGRA_GPIO(J, 0) >> + GPIO_ACTIVE_HIGH>; >> + ti,ac-detect-gpios = <&gpio >> + TEGRA_GPIO(J, 0) >> + GPIO_ACTIVE_HIGH>; >> + }; >> + >> + battery: sbs-battery@b { >> + compatible = "sbs,sbs-battery"; >> + reg = <0xb>; >> + sbs,i2c-retry-count = <2>; >> + sbs,poll-retry-count = <10>; >> + power-supplies = <&charger>; >> + }; >> + }; >> + }; >> + }; >> + >> + spi@0,7000da00 { >> + status = "okay"; >> + spi-max-frequency = <25000000>; >> + spi-flash@0 { >> + compatible = "winbond,w25q32dw"; >> + reg = <0>; >> + spi-max-frequency = <25000000>; >> + }; >> + }; >> + >> + pmc@0,7000e400 { >> + nvidia,invert-interrupt; >> + nvidia,suspend-mode = <0>; >> + nvidia,cpu-pwr-good-time = <500>; >> + nvidia,cpu-pwr-off-time = <300>; >> + nvidia,core-pwr-good-time = <641 3845>; >> + nvidia,core-pwr-off-time = <61036>; >> + nvidia,core-power-req-active-high; >> + nvidia,sys-clock-req-active-high; >> + }; >> + >> + hda@0,70030000 { >> + status = "okay"; >> + }; >> + >> + sdhci@0,700b0000 { >> + status = "okay"; >> + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; >> + bus-width = <4>; >> + no-1-8-v; >> + non-removable; >> + }; >> + >> + sdhci@0,700b0400 { >> + status = "okay"; >> + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; >> + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; >> + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; >> + bus-width = <4>; >> + no-1-8-v; >> + vqmmc-supply = <&vddio_sdmmc3>; >> + }; >> + >> + sdhci@0,700b0600 { >> + status = "okay"; >> + bus-width = <8>; >> + no-1-8-v; >> + non-removable; >> + }; >> + >> + ahub@0,70300000 { >> + i2s@0,70301100 { >> + status = "okay"; >> + }; >> + }; >> + >> + usb@0,7d000000 { >> + status = "okay"; >> + }; >> + >> + usb-phy@0,7d000000 { >> + status = "okay"; >> + vbus-supply = <&vdd_usb1_vbus>; >> + }; >> + >> + usb@0,7d004000 { >> + status = "okay"; >> + }; >> + >> + usb-phy@0,7d004000 { >> + status = "okay"; >> + vbus-supply = <&vdd_run_cam>; >> + }; >> + >> + usb@0,7d008000 { >> + status = "okay"; >> + }; >> + >> + usb-phy@0,7d008000 { >> + status = "okay"; >> + vbus-supply = <&vdd_usb3_vbus>; >> + }; >> + >> + backlight: backlight { >> + compatible = "pwm-backlight"; >> + >> + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; >> + power-supply = <&vdd_led>; >> + pwms = <&pwm 1 1000000>; >> + >> + default-brightness-level = <224>; >> + brightness-levels = >> + < 0 1 2 3 4 5 6 7 >> + 8 9 10 11 12 13 14 15 >> + 16 17 18 19 20 21 22 23 >> + 24 25 26 27 28 29 30 31 >> + 32 33 34 35 36 37 38 39 >> + 40 41 42 43 44 45 46 47 >> + 48 49 50 51 52 53 54 55 >> + 56 57 58 59 60 61 62 63 >> + 64 65 66 67 68 69 70 71 >> + 72 73 74 75 76 77 78 79 >> + 80 81 82 83 84 85 86 87 >> + 88 89 90 91 92 93 94 95 >> + 96 97 98 99 100 101 102 103 >> + 104 105 106 107 108 109 110 111 >> + 112 113 114 115 116 117 118 119 >> + 120 121 122 123 124 125 126 127 >> + 128 129 130 131 132 133 134 135 >> + 136 137 138 139 140 141 142 143 >> + 144 145 146 147 148 149 150 151 >> + 152 153 154 155 156 157 158 159 >> + 160 161 162 163 164 165 166 167 >> + 168 169 170 171 172 173 174 175 >> + 176 177 178 179 180 181 182 183 >> + 184 185 186 187 188 189 190 191 >> + 192 193 194 195 196 197 198 199 >> + 200 201 202 203 204 205 206 207 >> + 208 209 210 211 212 213 214 215 >> + 216 217 218 219 220 221 222 223 >> + 224 225 226 227 228 229 230 231 >> + 232 233 234 235 236 237 238 239 >> + 240 241 242 243 244 245 246 247 >> + 248 249 250 251 252 253 254 255 >> + 256>; >> + }; >> + >> + clocks { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + clk32k_in: clock@0 { >> + compatible = "fixed-clock"; >> + reg = <0>; >> + #clock-cells = <0>; >> + clock-frequency = <32768>; >> + }; >> + }; >> + >> + gpio-keys { >> + compatible = "gpio-keys"; >> + >> + lid { >> + label = "Lid"; >> + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; >> + linux,input-type = <5>; >> + linux,code = <0>; >> + debounce-interval = <1>; >> + gpio-key,wakeup; >> + }; >> + >> + power { >> + label = "Power"; >> + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; >> + linux,code = <KEY_POWER>; >> + debounce-interval = <30>; >> + gpio-key,wakeup; >> + }; >> + }; >> + >> + panel: panel { >> + compatible = "auo,b133xtn01", "simple-panel"; >> + >> + backlight = <&backlight>; >> + ddc-i2c-bus = <&dpaux>; >> + }; >> + >> + regulators { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + vdd_mux: regulator@0 { >> + compatible = "regulator-fixed"; >> + reg = <0>; >> + regulator-name = "+VDD_MUX"; >> + regulator-min-microvolt = <12000000>; >> + regulator-max-microvolt = <12000000>; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> + vdd_5v0_sys: regulator@1 { >> + compatible = "regulator-fixed"; >> + reg = <1>; >> + regulator-name = "+5V_SYS"; >> + regulator-min-microvolt = <5000000>; >> + regulator-max-microvolt = <5000000>; >> + regulator-always-on; >> + regulator-boot-on; >> + vin-supply = <&vdd_mux>; >> + }; >> + >> + vdd_3v3_sys: regulator@2 { >> + compatible = "regulator-fixed"; >> + reg = <2>; >> + regulator-name = "+3.3V_SYS"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + regulator-always-on; >> + regulator-boot-on; >> + vin-supply = <&vdd_mux>; >> + }; >> + >> + vdd_3v3_run: regulator@3 { >> + compatible = "regulator-fixed"; >> + reg = <3>; >> + regulator-name = "+3.3V_RUN"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + regulator-always-on; >> + regulator-boot-on; >> + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + vin-supply = <&vdd_3v3_sys>; >> + }; >> + >> + vdd_3v3_hdmi: regulator@4 { >> + compatible = "regulator-fixed"; >> + reg = <4>; >> + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + vin-supply = <&vdd_3v3_run>; >> + }; >> + >> + vdd_led: regulator@5 { >> + compatible = "regulator-fixed"; >> + reg = <5>; >> + regulator-name = "+VDD_LED"; >> + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + vin-supply = <&vdd_mux>; >> + }; >> + >> + vdd_5v0_ts: regulator@6 { >> + compatible = "regulator-fixed"; >> + reg = <6>; >> + regulator-name = "+5V_VDD_TS_SW"; >> + regulator-min-microvolt = <5000000>; >> + regulator-max-microvolt = <5000000>; >> + regulator-boot-on; >> + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + vin-supply = <&vdd_5v0_sys>; >> + }; >> + >> + vdd_usb1_vbus: regulator@7 { >> + compatible = "regulator-fixed"; >> + reg = <7>; >> + regulator-name = "+5V_USB_HS"; >> + regulator-min-microvolt = <5000000>; >> + regulator-max-microvolt = <5000000>; >> + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + gpio-open-drain; >> + vin-supply = <&vdd_5v0_sys>; >> + }; >> + >> + vdd_usb3_vbus: regulator@8 { >> + compatible = "regulator-fixed"; >> + reg = <8>; >> + regulator-name = "+5V_USB_SS"; >> + regulator-min-microvolt = <5000000>; >> + regulator-max-microvolt = <5000000>; >> + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + gpio-open-drain; >> + vin-supply = <&vdd_5v0_sys>; >> + }; >> + >> + vdd_3v3_panel: regulator@9 { >> + compatible = "regulator-fixed"; >> + reg = <9>; >> + regulator-name = "+3.3V_PANEL"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + vin-supply = <&vdd_3v3_run>; >> + }; >> + >> + vdd_3v3_lp0: regulator@10 { >> + compatible = "regulator-fixed"; >> + reg = <10>; >> + regulator-name = "+3.3V_LP0"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + /* >> + * TODO: find a way to wire this up with the USB EHCI >> + * controllers so that it can be enabled on demand. >> + */ >> + regulator-always-on; >> + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + vin-supply = <&vdd_3v3_sys>; >> + }; >> + >> + vdd_hdmi_pll: regulator@11 { >> + compatible = "regulator-fixed"; >> + reg = <11>; >> + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; >> + regulator-min-microvolt = <1050000>; >> + regulator-max-microvolt = <1050000>; >> + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; >> + vin-supply = <&vdd_1v05_run>; >> + }; >> + >> + vdd_5v0_hdmi: regulator@12 { >> + compatible = "regulator-fixed"; >> + reg = <12>; >> + regulator-name = "+5V_HDMI_CON"; >> + regulator-min-microvolt = <5000000>; >> + regulator-max-microvolt = <5000000>; >> + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + vin-supply = <&vdd_5v0_sys>; >> + }; >> + }; >> + >> + sound { >> + compatible = "nvidia,tegra-audio-max98090-venice2", >> + "nvidia,tegra-audio-max98090"; >> + nvidia,model = "NVIDIA Tegra Venice2"; >> + >> + nvidia,audio-routing = >> + "Headphones", "HPR", >> + "Headphones", "HPL", >> + "Speakers", "SPKR", >> + "Speakers", "SPKL", >> + "Mic Jack", "MICBIAS", >> + "DMICL", "Int Mic", >> + "DMICR", "Int Mic", >> + "IN34", "Mic Jack"; >> + >> + nvidia,i2s-controller = <&tegra_i2s1>; >> + nvidia,audio-codec = <&acodec>; >> + >> + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, >> + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, >> + <&tegra_car TEGRA124_CLK_EXTERN1>; >> + clock-names = "pll_a", "pll_a_out0", "mclk"; >> + >> + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; >> + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7) >> + GPIO_ACTIVE_HIGH>; >> + }; >> +}; >> + >> +#include "cros-ec-keyboard.dtsi" >> -- >> 2.1.0.rc2.206.gedb03e5 >> >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in >> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree 2015-01-14 0:32 ` Dylan Reid @ 2015-01-14 7:02 ` Tomeu Vizoso [not found] ` <CAAObsKBo13fEy72EQe3V409fEEYpw0kQss5UgaOhk=GOVEEeYg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 28+ messages in thread From: Tomeu Vizoso @ 2015-01-14 7:02 UTC (permalink / raw) To: Dylan Reid Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On 14 January 2015 at 01:32, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: > On Tue, Jan 13, 2015 at 9:49 AM, Tomeu Vizoso <tomeu-XCtybt49RKsYaV1qd6yewg@public.gmane.org> wrote: >> On 13 August 2014 at 03:56, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: >>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>> processor and is similar to the Venice2 reference platform. >>> >>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>> and work on the 1366x768 models. I haven't tried on the HD systems >>> yet. >> >> Hi Dylan, >> >> do you have any notes on how you tested audio? I have been fiddling a >> bit with amixer but haven't been able to get any sound from the >> speakers nor the headphones. > > I don't have any notes, and it's been a while since I tried it. To > the best of my knowledge, I loaded the UCM config from the ChromeOS > tree manually with alsaucm, then enabled/disabled headphones from > there. > > https://chromium.googlesource.com/chromiumos/third_party/adhd/+/master/ucm-config/nyan/NVIDIA%20Tegra%20Venice2/ > > The important stuff is all in the enable sequence of HiFi.conf > > Let me know if that helps. Thanks, it does work fine now. Will submit that conf file upstream. Tomeu ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <CAAObsKBo13fEy72EQe3V409fEEYpw0kQss5UgaOhk=GOVEEeYg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <CAAObsKBo13fEy72EQe3V409fEEYpw0kQss5UgaOhk=GOVEEeYg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2015-01-15 7:50 ` Thierry Reding 2015-01-15 12:18 ` Tomeu Vizoso 2015-01-15 17:18 ` Stephen Warren 0 siblings, 2 replies; 28+ messages in thread From: Thierry Reding @ 2015-01-15 7:50 UTC (permalink / raw) To: Tomeu Vizoso, Stephen Warren Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson [-- Attachment #1: Type: text/plain, Size: 1877 bytes --] On Wed, Jan 14, 2015 at 08:02:25AM +0100, Tomeu Vizoso wrote: > On 14 January 2015 at 01:32, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: > > On Tue, Jan 13, 2015 at 9:49 AM, Tomeu Vizoso <tomeu-XCtybt49RKsYaV1qd6yewg@public.gmane.org> wrote: > >> On 13 August 2014 at 03:56, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: > >>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 > >>> processor and is similar to the Venice2 reference platform. > >>> > >>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested > >>> and work on the 1366x768 models. I haven't tried on the HD systems > >>> yet. > >> > >> Hi Dylan, > >> > >> do you have any notes on how you tested audio? I have been fiddling a > >> bit with amixer but haven't been able to get any sound from the > >> speakers nor the headphones. > > > > I don't have any notes, and it's been a while since I tried it. To > > the best of my knowledge, I loaded the UCM config from the ChromeOS > > tree manually with alsaucm, then enabled/disabled headphones from > > there. > > > > https://chromium.googlesource.com/chromiumos/third_party/adhd/+/master/ucm-config/nyan/NVIDIA%20Tegra%20Venice2/ > > > > The important stuff is all in the enable sequence of HiFi.conf > > > > Let me know if that helps. > > Thanks, it does work fine now. Will submit that conf file upstream. Out of curiosity, where is "upstream" for UCM configuration files? It'd be interesting to collect files for other Tegra boards there. I find it rather tedious figuring out time and time again what control needs to be toggled to enable a certain output. Stephen, since you undoubtedly have the most experience with upstream audio, do you happen to know if we have something like that for the other upstream-supported boards? Thierry [-- Attachment #2: Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree 2015-01-15 7:50 ` Thierry Reding @ 2015-01-15 12:18 ` Tomeu Vizoso 2015-01-15 17:18 ` Stephen Warren 1 sibling, 0 replies; 28+ messages in thread From: Tomeu Vizoso @ 2015-01-15 12:18 UTC (permalink / raw) To: Thierry Reding Cc: Stephen Warren, Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On 15 January 2015 at 08:50, Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > On Wed, Jan 14, 2015 at 08:02:25AM +0100, Tomeu Vizoso wrote: >> On 14 January 2015 at 01:32, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: >> > On Tue, Jan 13, 2015 at 9:49 AM, Tomeu Vizoso <tomeu-XCtybt49RKsYaV1qd6yewg@public.gmane.org> wrote: >> >> On 13 August 2014 at 03:56, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: >> >>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> >>> processor and is similar to the Venice2 reference platform. >> >>> >> >>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> >>> and work on the 1366x768 models. I haven't tried on the HD systems >> >>> yet. >> >> >> >> Hi Dylan, >> >> >> >> do you have any notes on how you tested audio? I have been fiddling a >> >> bit with amixer but haven't been able to get any sound from the >> >> speakers nor the headphones. >> > >> > I don't have any notes, and it's been a while since I tried it. To >> > the best of my knowledge, I loaded the UCM config from the ChromeOS >> > tree manually with alsaucm, then enabled/disabled headphones from >> > there. >> > >> > https://chromium.googlesource.com/chromiumos/third_party/adhd/+/master/ucm-config/nyan/NVIDIA%20Tegra%20Venice2/ >> > >> > The important stuff is all in the enable sequence of HiFi.conf >> > >> > Let me know if that helps. >> >> Thanks, it does work fine now. Will submit that conf file upstream. > > Out of curiosity, where is "upstream" for UCM configuration files? It'd > be interesting to collect files for other Tegra boards there. I find it > rather tedious figuring out time and time again what control needs to be > toggled to enable a certain output. This is the best we have right now, TTBOMK. http://git.alsa-project.org/?p=alsa-lib.git;a=tree;f=src/conf/ucm Regards, Tomeu > Stephen, since you undoubtedly have the most experience with upstream > audio, do you happen to know if we have something like that for the > other upstream-supported boards? > > Thierry ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree 2015-01-15 7:50 ` Thierry Reding 2015-01-15 12:18 ` Tomeu Vizoso @ 2015-01-15 17:18 ` Stephen Warren 1 sibling, 0 replies; 28+ messages in thread From: Stephen Warren @ 2015-01-15 17:18 UTC (permalink / raw) To: Thierry Reding, Tomeu Vizoso Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On 01/15/2015 12:50 AM, Thierry Reding wrote: > On Wed, Jan 14, 2015 at 08:02:25AM +0100, Tomeu Vizoso wrote: >> On 14 January 2015 at 01:32, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: >>> On Tue, Jan 13, 2015 at 9:49 AM, Tomeu Vizoso <tomeu-XCtybt49RKsYaV1qd6yewg@public.gmane.org> wrote: >>>> On 13 August 2014 at 03:56, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: >>>>> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >>>>> processor and is similar to the Venice2 reference platform. >>>>> >>>>> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >>>>> and work on the 1366x768 models. I haven't tried on the HD systems >>>>> yet. >>>> >>>> Hi Dylan, >>>> >>>> do you have any notes on how you tested audio? I have been fiddling a >>>> bit with amixer but haven't been able to get any sound from the >>>> speakers nor the headphones. >>> >>> I don't have any notes, and it's been a while since I tried it. To >>> the best of my knowledge, I loaded the UCM config from the ChromeOS >>> tree manually with alsaucm, then enabled/disabled headphones from >>> there. >>> >>> https://chromium.googlesource.com/chromiumos/third_party/adhd/+/master/ucm-config/nyan/NVIDIA%20Tegra%20Venice2/ >>> >>> The important stuff is all in the enable sequence of HiFi.conf >>> >>> Let me know if that helps. >> >> Thanks, it does work fine now. Will submit that conf file upstream. > > Out of curiosity, where is "upstream" for UCM configuration files? It'd > be interesting to collect files for other Tegra boards there. I find it > rather tedious figuring out time and time again what control needs to be > toggled to enable a certain output. > > Stephen, since you undoubtedly have the most experience with upstream > audio, do you happen to know if we have something like that for the > other upstream-supported boards? I typically rely on the disto restoring settings from asound.state during boot, and saving them from HW during shutdown. I then put that asound.state on any filesystems I create. Adding UCM configurations sounds like it'd be a better alternative, presuming there's some automatic way for the distro to correlate the HW name to the UCM file name and automatically apply it during boot or audio startup. ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <1407894967-18300-1-git-send-email-dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> ` (2 preceding siblings ...) 2015-01-13 17:49 ` Tomeu Vizoso @ 2015-01-19 9:01 ` Tomeu Vizoso [not found] ` <CAAObsKA9EgdmqAe8JxJ=8nKJy6MsenHv8cpDO6fBiutBtgEpGw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 3 siblings, 1 reply; 28+ messages in thread From: Tomeu Vizoso @ 2015-01-19 9:01 UTC (permalink / raw) To: Dylan Reid Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren, Thierry Reding, Andrew Bresticker, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson On 13 August 2014 at 03:56, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: > The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 > processor and is similar to the Venice2 reference platform. > > The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested > and work on the 1366x768 models. I haven't tried on the HD systems > yet. > > WiFi does not yet work, it needs at least some PMIC changes to enable > the 32k clock. > > The elan trackpad is not yet functional but hopefully will be soon as > there are patches under review. > > There is also an issue on reboot because the TPM isn't reset. It will > cause the stock firmware to enter recovery mode. This can be worked > around by an EC-reset, press refresh and power at the same time. Hi Dylan, do you have any more information regarding this problem that could save me some investigation? Thanks, Tomeu ^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <CAAObsKA9EgdmqAe8JxJ=8nKJy6MsenHv8cpDO6fBiutBtgEpGw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree [not found] ` <CAAObsKA9EgdmqAe8JxJ=8nKJy6MsenHv8cpDO6fBiutBtgEpGw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2015-01-19 19:29 ` Andrew Bresticker 0 siblings, 0 replies; 28+ messages in thread From: Andrew Bresticker @ 2015-01-19 19:29 UTC (permalink / raw) To: Tomeu Vizoso Cc: Dylan Reid, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren, Thierry Reding, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Olof Johansson Hi Tomeu On Mon, Jan 19, 2015 at 1:01 AM, Tomeu Vizoso <tomeu-XCtybt49RKsYaV1qd6yewg@public.gmane.org> wrote: > On 13 August 2014 at 03:56, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote: >> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124 >> processor and is similar to the Venice2 reference platform. >> >> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested >> and work on the 1366x768 models. I haven't tried on the HD systems >> yet. >> >> WiFi does not yet work, it needs at least some PMIC changes to enable >> the 32k clock. >> >> The elan trackpad is not yet functional but hopefully will be soon as >> there are patches under review. >> >> There is also an issue on reboot because the TPM isn't reset. It will >> cause the stock firmware to enter recovery mode. This can be worked >> around by an EC-reset, press refresh and power at the same time. > > Hi Dylan, > > do you have any more information regarding this problem that could > save me some investigation? The PMC reset does not reset the TPM, so the reset pin (GPIO I5) must be toggled instead. -Andrew ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree
@ 2014-08-13 2:54 Dylan Reid
0 siblings, 0 replies; 28+ messages in thread
From: Dylan Reid @ 2014-08-13 2:54 UTC (permalink / raw)
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Stephen Warren, Thierry Reding, Andrew Bresticker,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org, Dylan Reid
I was just kidding about the second patch. I found a problem with
2/2. Please take this one alone and I'll continue working on wifi.
Thanks,
Dylan
On Tue, Aug 12, 2014 at 6:56 PM, Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote:
> The Acer Chromebook 13, codenamed "Big", contains an NVIDIA tegra124
> processor and is similar to the Venice2 reference platform.
>
> The keyboard, USB 2, audio, HDMI, sdcard and emmc have been tested
> and work on the 1366x768 models. I haven't tried on the HD systems
> yet.
>
> WiFi does not yet work, it needs at least some PMIC changes to enable
> the 32k clock.
>
> The elan trackpad is not yet functional but hopefully will be soon as
> there are patches under review.
>
> There is also an issue on reboot because the TPM isn't reset. It will
> cause the stock firmware to enter recovery mode. This can be worked
> around by an EC-reset, press refresh and power at the same time.
>
> Signed-off-by: Dylan Reid <dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/tegra124-big.dts | 1137 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 1138 insertions(+)
> create mode 100644 arch/arm/boot/dts/tegra124-big.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index acb6b42..b0ab6a6 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -439,6 +439,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
> tegra114-dalmore.dtb \
> tegra114-roth.dtb \
> tegra114-tn7.dtb \
> + tegra124-big.dtb \
> tegra124-jetson-tk1.dtb \
> tegra124-venice2.dtb
> dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
> diff --git a/arch/arm/boot/dts/tegra124-big.dts b/arch/arm/boot/dts/tegra124-big.dts
> new file mode 100644
> index 0000000..aa0cd9f
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra124-big.dts
> @@ -0,0 +1,1137 @@
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include "tegra124.dtsi"
> +
> +/ {
> + model = "Google Big";
> + compatible = "google,nyan-big", "nvidia,tegra124";
> +
> + aliases {
> + rtc0 = "/i2c@0,7000d000/pmic@40";
> + rtc1 = "/rtc@0,7000e000";
> + };
> +
> + memory {
> + reg = <0x0 0x80000000 0x0 0x80000000>;
> + };
> +
> + host1x@0,50000000 {
> + hdmi@0,54280000 {
> + status = "okay";
> +
> + vdd-supply = <&vdd_3v3_hdmi>;
> + pll-supply = <&vdd_hdmi_pll>;
> + hdmi-supply = <&vdd_5v0_hdmi>;
> +
> + nvidia,ddc-i2c-bus = <&hdmi_ddc>;
> + nvidia,hpd-gpio =
> + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
> + };
> +
> + sor@0,54540000 {
> + status = "okay";
> +
> + nvidia,dpaux = <&dpaux>;
> + nvidia,panel = <&panel>;
> + };
> +
> + dpaux: dpaux@0,545c0000 {
> + vdd-supply = <&vdd_3v3_panel>;
> + status = "okay";
> + };
> + };
> +
> + pinmux: pinmux@0,70000868 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinmux_default>;
> +
> + pinmux_default: common {
> + dap_mclk1_pw4 {
> + nvidia,pins = "dap_mclk1_pw4";
> + nvidia,function = "extperiph1";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + dap2_din_pa4 {
> + nvidia,pins = "dap2_din_pa4";
> + nvidia,function = "i2s1";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + dap2_dout_pa5 {
> + nvidia,pins = "dap2_dout_pa5",
> + "dap2_fs_pa2",
> + "dap2_sclk_pa3";
> + nvidia,function = "i2s1";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + dvfs_pwm_px0 {
> + nvidia,pins = "dvfs_pwm_px0",
> + "dvfs_clk_px2";
> + nvidia,function = "cldvfs";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + ulpi_clk_py0 {
> + nvidia,pins = "ulpi_clk_py0",
> + "ulpi_nxt_py2",
> + "ulpi_stp_py3";
> + nvidia,function = "spi1";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + ulpi_dir_py1 {
> + nvidia,pins = "ulpi_dir_py1";
> + nvidia,function = "spi1";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + cam_i2c_scl_pbb1 {
> + nvidia,pins = "cam_i2c_scl_pbb1",
> + "cam_i2c_sda_pbb2";
> + nvidia,function = "i2c3";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,lock = <TEGRA_PIN_DISABLE>;
> + nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> + };
> + gen2_i2c_scl_pt5 {
> + nvidia,pins = "gen2_i2c_scl_pt5",
> + "gen2_i2c_sda_pt6";
> + nvidia,function = "i2c2";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,lock = <TEGRA_PIN_DISABLE>;
> + nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> + };
> + pg4 {
> + nvidia,pins = "pg4",
> + "pg5",
> + "pg6",
> + "pi3";
> + nvidia,function = "spi4";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + pg7 {
> + nvidia,pins = "pg7";
> + nvidia,function = "spi4";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + ph1 {
> + nvidia,pins = "ph1";
> + nvidia,function = "pwm1";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + pk0 {
> + nvidia,pins = "pk0",
> + "kb_row15_ps7",
> + "clk_32k_out_pa0";
> + nvidia,function = "soc";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + sdmmc1_clk_pz0 {
> + nvidia,pins = "sdmmc1_clk_pz0";
> + nvidia,function = "sdmmc1";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + sdmmc1_cmd_pz1 {
> + nvidia,pins = "sdmmc1_cmd_pz1",
> + "sdmmc1_dat0_py7",
> + "sdmmc1_dat1_py6",
> + "sdmmc1_dat2_py5",
> + "sdmmc1_dat3_py4";
> + nvidia,function = "sdmmc1";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + sdmmc3_clk_pa6 {
> + nvidia,pins = "sdmmc3_clk_pa6";
> + nvidia,function = "sdmmc3";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + sdmmc3_cmd_pa7 {
> + nvidia,pins = "sdmmc3_cmd_pa7",
> + "sdmmc3_dat0_pb7",
> + "sdmmc3_dat1_pb6",
> + "sdmmc3_dat2_pb5",
> + "sdmmc3_dat3_pb4",
> + "kb_col4_pq4",
> + "sdmmc3_clk_lb_out_pee4",
> + "sdmmc3_clk_lb_in_pee5",
> + "sdmmc3_cd_n_pv2";
> + nvidia,function = "sdmmc3";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + sdmmc4_clk_pcc4 {
> + nvidia,pins = "sdmmc4_clk_pcc4";
> + nvidia,function = "sdmmc4";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + sdmmc4_cmd_pt7 {
> + nvidia,pins = "sdmmc4_cmd_pt7",
> + "sdmmc4_dat0_paa0",
> + "sdmmc4_dat1_paa1",
> + "sdmmc4_dat2_paa2",
> + "sdmmc4_dat3_paa3",
> + "sdmmc4_dat4_paa4",
> + "sdmmc4_dat5_paa5",
> + "sdmmc4_dat6_paa6",
> + "sdmmc4_dat7_paa7";
> + nvidia,function = "sdmmc4";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + pwr_i2c_scl_pz6 {
> + nvidia,pins = "pwr_i2c_scl_pz6",
> + "pwr_i2c_sda_pz7";
> + nvidia,function = "i2cpwr";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,lock = <TEGRA_PIN_DISABLE>;
> + nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> + };
> + jtag_rtck {
> + nvidia,pins = "jtag_rtck";
> + nvidia,function = "rtck";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + clk_32k_in {
> + nvidia,pins = "clk_32k_in";
> + nvidia,function = "clk";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + core_pwr_req {
> + nvidia,pins = "core_pwr_req";
> + nvidia,function = "pwron";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + cpu_pwr_req {
> + nvidia,pins = "cpu_pwr_req";
> + nvidia,function = "cpu";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + pwr_int_n {
> + nvidia,pins = "pwr_int_n";
> + nvidia,function = "pmi";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + reset_out_n {
> + nvidia,pins = "reset_out_n";
> + nvidia,function = "reset_out_n";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + clk3_out_pee0 {
> + nvidia,pins = "clk3_out_pee0";
> + nvidia,function = "extperiph3";
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + gen1_i2c_sda_pc5 {
> + nvidia,pins = "gen1_i2c_sda_pc5",
> + "gen1_i2c_scl_pc4";
> + nvidia,function = "i2c1";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,lock = <TEGRA_PIN_DISABLE>;
> + nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> + };
> + hdmi_cec_pee3 {
> + nvidia,pins = "hdmi_cec_pee3";
> + nvidia,function = "cec";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,lock = <TEGRA_PIN_DISABLE>;
> + nvidia,open-drain = <TEGRA_PIN_DISABLE>;
> + };
> + hdmi_int_pn7 {
> + nvidia,pins = "hdmi_int_pn7";
> + nvidia,function = "rsvd1";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + ddc_scl_pv4 {
> + nvidia,pins = "ddc_scl_pv4",
> + "ddc_sda_pv5";
> + nvidia,function = "i2c4";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,lock = <TEGRA_PIN_DISABLE>;
> + nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
> + };
> + kb_row10_ps2 {
> + nvidia,pins = "kb_row10_ps2";
> + nvidia,function = "uarta";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + kb_row9_ps1 {
> + nvidia,pins = "kb_row9_ps1";
> + nvidia,function = "uarta";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + usb_vbus_en0_pn4 {
> + nvidia,pins = "usb_vbus_en0_pn4",
> + "usb_vbus_en1_pn5";
> + nvidia,function = "usb";
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,lock = <TEGRA_PIN_DISABLE>;
> + nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> + };
> + drive_sdio1 {
> + nvidia,pins = "drive_sdio1";
> + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
> + nvidia,schmitt = <TEGRA_PIN_DISABLE>;
> + nvidia,pull-down-strength = <36>;
> + nvidia,pull-up-strength = <20>;
> + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
> + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
> + };
> + drive_sdio3 {
> + nvidia,pins = "drive_sdio3";
> + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
> + nvidia,schmitt = <TEGRA_PIN_DISABLE>;
> + nvidia,pull-down-strength = <22>;
> + nvidia,pull-up-strength = <36>;
> + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
> + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
> + };
> + drive_gma {
> + nvidia,pins = "drive_gma";
> + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
> + nvidia,schmitt = <TEGRA_PIN_DISABLE>;
> + nvidia,pull-down-strength = <2>;
> + nvidia,pull-up-strength = <1>;
> + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
> + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
> + nvidia,drive-type = <1>;
> + };
> + codec_irq_l {
> + nvidia,pins = "ph4";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + lcd_bl_en {
> + nvidia,pins = "ph2";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + touch_irq_l {
> + nvidia,pins = "gpio_w3_aud_pw3";
> + nvidia,function = "spi6";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + tpm_davint_l {
> + nvidia,pins = "ph6";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + ts_irq_l {
> + nvidia,pins = "pk2";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + ts_reset_l {
> + nvidia,pins = "pk4";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + ts_shdn_l {
> + nvidia,pins = "pk1";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + ph7 {
> + nvidia,pins = "ph7";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + kb_col0_ap {
> + nvidia,pins = "kb_col0_pq0";
> + nvidia,function = "rsvd4";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + lid_open {
> + nvidia,pins = "kb_row4_pr4";
> + nvidia,function = "rsvd3";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + en_vdd_sd {
> + nvidia,pins = "kb_row0_pr0";
> + nvidia,function = "rsvd4";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + ac_ok {
> + nvidia,pins = "pj0";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + sensor_irq_l {
> + nvidia,pins = "pi6";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + wifi_en {
> + nvidia,pins = "gpio_x7_aud_px7";
> + nvidia,function = "rsvd4";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + en_vdd_bl {
> + nvidia,pins = "dap3_dout_pp2";
> + nvidia,function = "i2s2";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + en_vdd_hdmi {
> + nvidia,pins = "spdif_in_pk6";
> + nvidia,function = "spdif";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + soc_warm_reset_l {
> + nvidia,pins = "pi5";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + hp_det_l {
> + nvidia,pins = "pi7";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + mic_det_l {
> + nvidia,pins = "kb_row7_pr7";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + };
> +
> + serial@0,70006000 {
> + status = "okay";
> + };
> +
> + pwm: pwm@0,7000a000 {
> + status = "okay";
> + };
> +
> + i2c@0,7000c000 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + acodec: audio-codec@10 {
> + compatible = "maxim,max98090";
> + reg = <0x10>;
> + interrupt-parent = <&gpio>;
> + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
> + };
> +
> + temperature-sensor@4c {
> + compatible = "ti,tmp451";
> + reg = <0x4c>;
> + interrupt-parent = <&gpio>;
> + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> + };
> +
> + i2c@0,7000c400 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@0,7000c500 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + tpm@20 {
> + compatible = "infineon,slb9645tt";
> + reg = <0x20>;
> + };
> + };
> +
> + hdmi_ddc: i2c@0,7000c700 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c@0,7000d000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + pmic: pmic@40 {
> + compatible = "ams,as3722";
> + reg = <0x40>;
> + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
> +
> + ams,system-power-controller;
> +
> + #interrupt-cells = <2>;
> + interrupt-controller;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&as3722_default>;
> +
> + as3722_default: pinmux {
> + gpio0 {
> + pins = "gpio0";
> + function = "gpio";
> + bias-pull-down;
> + };
> +
> + gpio1 {
> + pins = "gpio1";
> + function = "gpio";
> + bias-pull-up;
> + };
> +
> + gpio2_4_7 {
> + pins = "gpio2", "gpio4", "gpio7";
> + function = "gpio";
> + bias-pull-up;
> + };
> +
> + gpio3_6 {
> + pins = "gpio3", "gpio6";
> + bias-high-impedance;
> + };
> +
> + gpio5 {
> + pins = "gpio5";
> + function = "clk32k-out";
> + bias-pull-down;
> + };
> + };
> +
> + regulators {
> + vsup-sd2-supply = <&vdd_5v0_sys>;
> + vsup-sd3-supply = <&vdd_5v0_sys>;
> + vsup-sd4-supply = <&vdd_5v0_sys>;
> + vsup-sd5-supply = <&vdd_5v0_sys>;
> + vin-ldo0-supply = <&vdd_1v35_lp0>;
> + vin-ldo1-6-supply = <&vdd_3v3_run>;
> + vin-ldo2-5-7-supply = <&vddio_1v8>;
> + vin-ldo3-4-supply = <&vdd_3v3_sys>;
> + vin-ldo9-10-supply = <&vdd_5v0_sys>;
> + vin-ldo11-supply = <&vdd_3v3_run>;
> +
> + sd0 {
> + regulator-name = "+VDD_CPU_AP";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-min-microamp = <3500000>;
> + regulator-max-microamp = <3500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + ams,ext-control = <2>;
> + };
> +
> + sd1 {
> + regulator-name = "+VDD_CORE";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-min-microamp = <2500000>;
> + regulator-max-microamp = <4000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + ams,ext-control = <1>;
> + };
> +
> + vdd_1v35_lp0: sd2 {
> + regulator-name = "+1.35V_LP0(sd2)";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + sd3 {
> + regulator-name = "+1.35V_LP0(sd3)";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_1v05_run: sd4 {
> + regulator-name = "+1.05V_RUN";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + vddio_1v8: sd5 {
> + regulator-name = "+1.8V_VDDIO";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sd6 {
> + regulator-name = "+VDD_GPU_AP";
> + regulator-min-microvolt = <650000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-min-microamp = <3500000>;
> + regulator-max-microamp = <3500000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo0 {
> + regulator-name = "+1.05V_RUN_AVDD";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + regulator-boot-on;
> + regulator-always-on;
> + ams,ext-control = <1>;
> + };
> +
> + ldo1 {
> + regulator-name = "+1.8V_RUN_CAM";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo2 {
> + regulator-name = "+1.2V_GEN_AVDD";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo3 {
> + regulator-name = "+1.00V_LP0_VDD_RTC";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + ams,enable-tracking;
> + };
> +
> + vdd_run_cam: ldo4 {
> + regulator-name = "+3.3V_RUN_CAM";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo5 {
> + regulator-name = "+1.2V_RUN_CAM_FRONT";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + vddio_sdmmc3: ldo6 {
> + regulator-name = "+VDDIO_SDMMC3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo7 {
> + regulator-name = "+1.05V_RUN_CAM_REAR";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + ldo9 {
> + regulator-name = "+2.8V_RUN_TOUCH";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo10 {
> + regulator-name = "+2.8V_RUN_CAM_AF";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo11 {
> + regulator-name = "+1.8V_RUN_VPP_FUSE";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> + };
> + };
> + };
> +
> + spi@0,7000d400 {
> + status = "okay";
> +
> + cros_ec: cros-ec@0 {
> + compatible = "google,cros-ec-spi";
> + spi-max-frequency = <3000000>;
> + interrupt-parent = <&gpio>;
> + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
> + reg = <0>;
> +
> + google,cros-ec-spi-msg-delay = <2000>;
> +
> + i2c-tunnel {
> + compatible = "google,cros-ec-i2c-tunnel";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + google,remote-bus = <0>;
> +
> + charger: bq24735@9 {
> + compatible = "ti,bq24735";
> + reg = <0x9>;
> + interrupt-parent = <&gpio>;
> + interrupts = <TEGRA_GPIO(J, 0)
> + GPIO_ACTIVE_HIGH>;
> + ti,ac-detect-gpios = <&gpio
> + TEGRA_GPIO(J, 0)
> + GPIO_ACTIVE_HIGH>;
> + };
> +
> + battery: sbs-battery@b {
> + compatible = "sbs,sbs-battery";
> + reg = <0xb>;
> + sbs,i2c-retry-count = <2>;
> + sbs,poll-retry-count = <10>;
> + power-supplies = <&charger>;
> + };
> + };
> + };
> + };
> +
> + spi@0,7000da00 {
> + status = "okay";
> + spi-max-frequency = <25000000>;
> + spi-flash@0 {
> + compatible = "winbond,w25q32dw";
> + reg = <0>;
> + spi-max-frequency = <25000000>;
> + };
> + };
> +
> + pmc@0,7000e400 {
> + nvidia,invert-interrupt;
> + nvidia,suspend-mode = <0>;
> + nvidia,cpu-pwr-good-time = <500>;
> + nvidia,cpu-pwr-off-time = <300>;
> + nvidia,core-pwr-good-time = <641 3845>;
> + nvidia,core-pwr-off-time = <61036>;
> + nvidia,core-power-req-active-high;
> + nvidia,sys-clock-req-active-high;
> + };
> +
> + hda@0,70030000 {
> + status = "okay";
> + };
> +
> + sdhci@0,700b0000 {
> + status = "okay";
> + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
> + bus-width = <4>;
> + no-1-8-v;
> + non-removable;
> + };
> +
> + sdhci@0,700b0400 {
> + status = "okay";
> + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
> + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
> + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + no-1-8-v;
> + vqmmc-supply = <&vddio_sdmmc3>;
> + };
> +
> + sdhci@0,700b0600 {
> + status = "okay";
> + bus-width = <8>;
> + no-1-8-v;
> + non-removable;
> + };
> +
> + ahub@0,70300000 {
> + i2s@0,70301100 {
> + status = "okay";
> + };
> + };
> +
> + usb@0,7d000000 {
> + status = "okay";
> + };
> +
> + usb-phy@0,7d000000 {
> + status = "okay";
> + vbus-supply = <&vdd_usb1_vbus>;
> + };
> +
> + usb@0,7d004000 {
> + status = "okay";
> + };
> +
> + usb-phy@0,7d004000 {
> + status = "okay";
> + vbus-supply = <&vdd_run_cam>;
> + };
> +
> + usb@0,7d008000 {
> + status = "okay";
> + };
> +
> + usb-phy@0,7d008000 {
> + status = "okay";
> + vbus-supply = <&vdd_usb3_vbus>;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> +
> + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
> + power-supply = <&vdd_led>;
> + pwms = <&pwm 1 1000000>;
> +
> + default-brightness-level = <224>;
> + brightness-levels =
> + < 0 1 2 3 4 5 6 7
> + 8 9 10 11 12 13 14 15
> + 16 17 18 19 20 21 22 23
> + 24 25 26 27 28 29 30 31
> + 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47
> + 48 49 50 51 52 53 54 55
> + 56 57 58 59 60 61 62 63
> + 64 65 66 67 68 69 70 71
> + 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87
> + 88 89 90 91 92 93 94 95
> + 96 97 98 99 100 101 102 103
> + 104 105 106 107 108 109 110 111
> + 112 113 114 115 116 117 118 119
> + 120 121 122 123 124 125 126 127
> + 128 129 130 131 132 133 134 135
> + 136 137 138 139 140 141 142 143
> + 144 145 146 147 148 149 150 151
> + 152 153 154 155 156 157 158 159
> + 160 161 162 163 164 165 166 167
> + 168 169 170 171 172 173 174 175
> + 176 177 178 179 180 181 182 183
> + 184 185 186 187 188 189 190 191
> + 192 193 194 195 196 197 198 199
> + 200 201 202 203 204 205 206 207
> + 208 209 210 211 212 213 214 215
> + 216 217 218 219 220 221 222 223
> + 224 225 226 227 228 229 230 231
> + 232 233 234 235 236 237 238 239
> + 240 241 242 243 244 245 246 247
> + 248 249 250 251 252 253 254 255
> + 256>;
> + };
> +
> + clocks {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + clk32k_in: clock@0 {
> + compatible = "fixed-clock";
> + reg = <0>;
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + lid {
> + label = "Lid";
> + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
> + linux,input-type = <5>;
> + linux,code = <0>;
> + debounce-interval = <1>;
> + gpio-key,wakeup;
> + };
> +
> + power {
> + label = "Power";
> + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + debounce-interval = <30>;
> + gpio-key,wakeup;
> + };
> + };
> +
> + panel: panel {
> + compatible = "auo,b133xtn01", "simple-panel";
> +
> + backlight = <&backlight>;
> + ddc-i2c-bus = <&dpaux>;
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdd_mux: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "+VDD_MUX";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_5v0_sys: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "+5V_SYS";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <&vdd_mux>;
> + };
> +
> + vdd_3v3_sys: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "+3.3V_SYS";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <&vdd_mux>;
> + };
> +
> + vdd_3v3_run: regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + regulator-name = "+3.3V_RUN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&vdd_3v3_sys>;
> + };
> +
> + vdd_3v3_hdmi: regulator@4 {
> + compatible = "regulator-fixed";
> + reg = <4>;
> + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vdd_3v3_run>;
> + };
> +
> + vdd_led: regulator@5 {
> + compatible = "regulator-fixed";
> + reg = <5>;
> + regulator-name = "+VDD_LED";
> + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&vdd_mux>;
> + };
> +
> + vdd_5v0_ts: regulator@6 {
> + compatible = "regulator-fixed";
> + reg = <6>;
> + regulator-name = "+5V_VDD_TS_SW";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&vdd_5v0_sys>;
> + };
> +
> + vdd_usb1_vbus: regulator@7 {
> + compatible = "regulator-fixed";
> + reg = <7>;
> + regulator-name = "+5V_USB_HS";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + gpio-open-drain;
> + vin-supply = <&vdd_5v0_sys>;
> + };
> +
> + vdd_usb3_vbus: regulator@8 {
> + compatible = "regulator-fixed";
> + reg = <8>;
> + regulator-name = "+5V_USB_SS";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + gpio-open-drain;
> + vin-supply = <&vdd_5v0_sys>;
> + };
> +
> + vdd_3v3_panel: regulator@9 {
> + compatible = "regulator-fixed";
> + reg = <9>;
> + regulator-name = "+3.3V_PANEL";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&vdd_3v3_run>;
> + };
> +
> + vdd_3v3_lp0: regulator@10 {
> + compatible = "regulator-fixed";
> + reg = <10>;
> + regulator-name = "+3.3V_LP0";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + /*
> + * TODO: find a way to wire this up with the USB EHCI
> + * controllers so that it can be enabled on demand.
> + */
> + regulator-always-on;
> + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&vdd_3v3_sys>;
> + };
> +
> + vdd_hdmi_pll: regulator@11 {
> + compatible = "regulator-fixed";
> + reg = <11>;
> + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
> + vin-supply = <&vdd_1v05_run>;
> + };
> +
> + vdd_5v0_hdmi: regulator@12 {
> + compatible = "regulator-fixed";
> + reg = <12>;
> + regulator-name = "+5V_HDMI_CON";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&vdd_5v0_sys>;
> + };
> + };
> +
> + sound {
> + compatible = "nvidia,tegra-audio-max98090-venice2",
> + "nvidia,tegra-audio-max98090";
> + nvidia,model = "NVIDIA Tegra Venice2";
> +
> + nvidia,audio-routing =
> + "Headphones", "HPR",
> + "Headphones", "HPL",
> + "Speakers", "SPKR",
> + "Speakers", "SPKL",
> + "Mic Jack", "MICBIAS",
> + "DMICL", "Int Mic",
> + "DMICR", "Int Mic",
> + "IN34", "Mic Jack";
> +
> + nvidia,i2s-controller = <&tegra_i2s1>;
> + nvidia,audio-codec = <&acodec>;
> +
> + clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
> + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
> + <&tegra_car TEGRA124_CLK_EXTERN1>;
> + clock-names = "pll_a", "pll_a_out0", "mclk";
> +
> + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
> + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7)
> + GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +#include "cros-ec-keyboard.dtsi"
> --
> 2.1.0.rc2.206.gedb03e5
>
^ permalink raw reply [flat|nested] 28+ messages in threadend of thread, other threads:[~2015-01-19 19:29 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
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2014-08-13 1:56 [PATCH 1/2] ARM: tegra: add Acer Chromebook 13 device tree Dylan Reid
[not found] ` <1407894967-18300-1-git-send-email-dgreid-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-08-13 8:53 ` Thierry Reding
2014-08-13 16:23 ` Andrew Bresticker
2014-08-13 16:51 ` Olof Johansson
[not found] ` <CAOesGMg2uZ8-ypeuSXJoSN3mz6jBjNwLbTo9EiXOf2D7iVCfiQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-13 16:57 ` Stephen Warren
2014-08-13 16:51 ` Stephen Warren
[not found] ` <53EB9786.6010809-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-08-13 16:55 ` Olof Johansson
2014-08-13 17:04 ` Andrew Bresticker
[not found] ` <CAL1qeaGxcp4okVTYCMj0zMh-4HzsGLBvngv0+A1m8o3sZPDj2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-13 17:12 ` Stephen Warren
[not found] ` <53EB9C61.1070406-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-08-13 17:17 ` Andrew Bresticker
2014-08-13 18:42 ` Dylan Reid
2014-08-13 17:10 ` Stephen Warren
[not found] ` <53EB9BF0.9010002-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-08-13 17:23 ` Olof Johansson
[not found] ` <CAOesGMhAzx==sXnHBg4dhAtO3=JP-s-MmzujskctA=7OUC0uRg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-13 17:31 ` Stephen Warren
[not found] ` <53EBA0ED.30607-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-08-13 17:37 ` Olof Johansson
[not found] ` <CAOesGMgeLbuURwA1VVxkLp=vH9PB_VdUHFJthH=ae-_ZDVYyAA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-13 20:17 ` Stephen Warren
2014-08-13 19:07 ` Dylan Reid
2014-08-13 19:56 ` Stephen Warren
[not found] ` <53EBC2EC.1010300-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-08-14 8:40 ` Dylan Reid
2015-01-13 17:49 ` Tomeu Vizoso
[not found] ` <CAAObsKCbJLwEHeiv3DbCwsiVSZ0VDGzU84+ipPKJQZajx+KiuQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-01-14 0:32 ` Dylan Reid
2015-01-14 7:02 ` Tomeu Vizoso
[not found] ` <CAAObsKBo13fEy72EQe3V409fEEYpw0kQss5UgaOhk=GOVEEeYg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-01-15 7:50 ` Thierry Reding
2015-01-15 12:18 ` Tomeu Vizoso
2015-01-15 17:18 ` Stephen Warren
2015-01-19 9:01 ` Tomeu Vizoso
[not found] ` <CAAObsKA9EgdmqAe8JxJ=8nKJy6MsenHv8cpDO6fBiutBtgEpGw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-01-19 19:29 ` Andrew Bresticker
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2014-08-13 2:54 Dylan Reid
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