[PATCH] pinctrl: tegra: Add APB misc MIPI pad control

[PATCH] pinctrl: tegra: Add APB misc MIPI pad control

[Sean Paul]

This patch adds MIPI CSI/DSIB pad control mux register
from the APB misc block to tegra pinctrl.

Without writing to this register, the dsib pads are
muxed as csi, and cannot be used.

The register is not yet documented in the TRM, here is
the description:

70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
	[31:02] RESERVED
	[01:01] DSIB_MODE       [CSI=0,DSIB=1]
	[00:00] RESERVED

Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
 drivers/pinctrl/pinctrl-tegra124.c | 48 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index e80797e..9a3359f 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -224,6 +224,7 @@
 #define TEGRA_PIN_OWR				_PIN(5)
 #define TEGRA_PIN_CLK_32K_IN			_PIN(6)
 #define TEGRA_PIN_JTAG_RTCK			_PIN(7)
+#define TEGRA_PIN_CSI_DSIB			_PIN(8)
 
 static const struct pinctrl_pin_desc tegra124_pins[] = {
 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
@@ -417,6 +418,7 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
 	PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 	PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
+	PINCTRL_PIN(TEGRA_PIN_CSI_DSIB, "CSI_DSIB"),
 };
 
 static const unsigned clk_32k_out_pa0_pins[] = {
@@ -1495,6 +1497,10 @@ static const unsigned drive_ao4_pins[] = {
 	TEGRA_PIN_JTAG_RTCK,
 };
 
+static const unsigned csi_dsib_pins[] = {
+	TEGRA_PIN_CSI_DSIB,
+};
+
 enum tegra_mux {
 	TEGRA_MUX_BLINK,
 	TEGRA_MUX_CCLA,
@@ -1580,6 +1586,16 @@ enum tegra_mux {
 	TEGRA_MUX_VI_ALT3,
 	TEGRA_MUX_VIMCLK2,
 	TEGRA_MUX_VIMCLK2_ALT,
+	TEGRA_MUX_CSI,
+	TEGRA_MUX_DSIB,
+};
+
+static const char * const csi_groups[] = {
+	"csi_dsib",
+};
+
+static const char * const dsib_groups[] = {
+	"csi_dsib",
 };
 
 #define FUNCTION(fname)					\
@@ -1672,10 +1688,13 @@ static struct tegra_function tegra124_functions[] = {
 	FUNCTION(vi_alt3),
 	FUNCTION(vimclk2),
 	FUNCTION(vimclk2_alt),
+	FUNCTION(csi),
+	FUNCTION(dsib),
 };
 
 #define DRV_PINGROUP_REG_A		0x868	/* bank 0 */
 #define PINGROUP_REG_A			0x3000	/* bank 1 */
+#define APB_MISC_PINGROUP_REG_A		0x820	/* bank 2 */
 
 #define PINGROUP_REG(r)			((r) - PINGROUP_REG_A)
 
@@ -1744,6 +1763,32 @@ static struct tegra_function tegra124_functions[] = {
 		.drvtype_bit = PINGROUP_BIT_##drvtype(6),		\
 	}
 
+#define APB_MISC_PINGROUP_REG_Y(r)	((r) - APB_MISC_PINGROUP_REG_A)
+
+#define APB_MISC_PINGROUP(pg_name, r, b, f0, f1, f_safe)		\
+	{								\
+		.name = #pg_name,					\
+		.pins = pg_name##_pins,					\
+		.npins = ARRAY_SIZE(pg_name##_pins),			\
+		.funcs = {						\
+			TEGRA_MUX_ ## f0,				\
+			TEGRA_MUX_ ## f1,				\
+		},							\
+		.func_safe = TEGRA_MUX_ ## f_safe,			\
+		.mux_reg = APB_MISC_PINGROUP_REG_Y(r),			\
+		.mux_bank = 2,						\
+		.mux_bit = b,						\
+		.pupd_reg = -1,						\
+		.tri_reg = -1,						\
+		.einput_reg = -1,					\
+		.odrain_reg = -1,					\
+		.lock_reg = -1,						\
+		.ioreset_reg = -1,					\
+		.rcv_sel_reg = -1,					\
+		.drv_reg = -1,						\
+		.drvtype_reg = -1,					\
+	}
+
 static const struct tegra_pingroup tegra124_groups[] = {
 	/*       pg_name,                f0,         f1,         f2,           f3,          r,      od, ior, rcv_sel */
 	PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        0x3000, N,   N,  N),
@@ -1979,6 +2024,9 @@ static const struct tegra_pingroup tegra124_groups[] = {
 	DRV_PINGROUP(hv0,         0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
 	DRV_PINGROUP(sdio4,       0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
 	DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
+
+       /*			pg_name,	r	b	f0,	f1,	f_safe */
+       APB_MISC_PINGROUP(	csi_dsib,	0x820,	1,	CSI,	DSIB,	DSIB)
 };
 
 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
-- 
2.0.0

Re: [PATCH] pinctrl: tegra: Add APB misc MIPI pad control

[Stephen Warren]

On 09/02/2014 11:18 AM, Sean Paul wrote:
> This patch adds MIPI CSI/DSIB pad control mux register
> from the APB misc block to tegra pinctrl.
>
> Without writing to this register, the dsib pads are
> muxed as csi, and cannot be used.
>
> The register is not yet documented in the TRM, here is
> the description:
>
> 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
> 	[31:02] RESERVED
> 	[01:01] DSIB_MODE       [CSI=0,DSIB=1]
> 	[00:00] RESERVED

That's a very unfortunate HW design, but oh well:-(

I slightly wonder whether it's legitimate to even consider that register 
part of the pinmux controller; I certainly don't see any mention of it 
in the pinmux spreadsheets. It feels like some unrelated bolt-on 
feature. Still, I suppose requiring a separate driver for it just 
because the registers aren't all nicely grouped is a bit silly. At least 
a quick glance implies there aren't any other missing cases like this, 
so we shouldn't need to add any more later.

I don't suppose there's any chance you could update:
git://github.com/NVIDIA/tegra-pinmux-scripts.git
with an equivalent change?

> diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c

> +#define TEGRA_PIN_CSI_DSIB			_PIN(8)

Is that actually the name of the pin on the Tegra package? I don't see 
anything like that the board schematic I have.

>   #define DRV_PINGROUP_REG_A		0x868	/* bank 0 */
>   #define PINGROUP_REG_A			0x3000	/* bank 1 */
> +#define APB_MISC_PINGROUP_REG_A		0x820	/* bank 2 */

In order for that to work, an extra reg entry will be required in DT so 
that registers in bank 2 can be accessed. I would expect this patch (or 
series) to contain an addition to 
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt to 
mention this. I assume you'll send a patch to 
arch/arm/boot/dts/tegra124.dtsi separately to add that entry.

> +#define APB_MISC_PINGROUP(pg_name, r, b, f0, f1, f_safe)		\

f_safe isn't present in any of the upstream Tegra pinctrl drivers any 
more, so that parameter isn't needed any more...

> +	{								\
> +		.name = #pg_name,					\
> +		.pins = pg_name##_pins,					\
> +		.npins = ARRAY_SIZE(pg_name##_pins),			\
> +		.funcs = {						\
> +			TEGRA_MUX_ ## f0,				\
> +			TEGRA_MUX_ ## f1,				\
> +		},							\
> +		.func_safe = TEGRA_MUX_ ## f_safe,			\

... and I don't think that line will even compile, since that field 
doesn't exist?

All 4 entries in .funcs[] should be initialized too. If two don't make 
sense, then they should at least be hard-coded to TEGRA_MUX_RSVD3/4. It 
would be nice if the driver knew that this pin only had two valid mux 
options, but I suppose updating the code to handle that special case 
isn't really worth it.

>   	DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
> +
> +       /*			pg_name,	r	b	f0,	f1,	f_safe */
> +       APB_MISC_PINGROUP(	csi_dsib,	0x820,	1,	CSI,	DSIB,	DSIB)
>   };

Can you make the indentation of the added lines consistent here. The 
existing code uses a TAB at the start of the line (but the patch uses 
spaces), and spaces internally (but the patch uses TABs) so columns 
don't have to waste space being TAB aligned. The pg_name column should 
be nestled right against the opening (, without any intervening space.

Re: [PATCH] pinctrl: tegra: Add APB misc MIPI pad control

[Sean Paul]

On Tue, Sep 2, 2014 at 4:31 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 09/02/2014 11:18 AM, Sean Paul wrote:
>>
>> This patch adds MIPI CSI/DSIB pad control mux register
>> from the APB misc block to tegra pinctrl.
>>
>> Without writing to this register, the dsib pads are
>> muxed as csi, and cannot be used.
>>
>> The register is not yet documented in the TRM, here is
>> the description:
>>
>> 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
>>         [31:02] RESERVED
>>         [01:01] DSIB_MODE       [CSI=0,DSIB=1]
>>         [00:00] RESERVED
>
>
> That's a very unfortunate HW design, but oh well:-(
>
> I slightly wonder whether it's legitimate to even consider that register
> part of the pinmux controller; I certainly don't see any mention of it in
> the pinmux spreadsheets. It feels like some unrelated bolt-on feature.
> Still, I suppose requiring a separate driver for it just because the
> registers aren't all nicely grouped is a bit silly. At least a quick glance
> implies there aren't any other missing cases like this, so we shouldn't need
> to add any more later.
>

Yeah, the hw is unfortunate. It doesn't feel like this solution was Plan A :-)

> I don't suppose there's any chance you could update:
> git://github.com/NVIDIA/tegra-pinmux-scripts.git
> with an equivalent change?
>

Sure, I can do that.

>> diff --git a/drivers/pinctrl/pinctrl-tegra124.c
>> b/drivers/pinctrl/pinctrl-tegra124.c
>
>
>> +#define TEGRA_PIN_CSI_DSIB                     _PIN(8)
>
>
> Is that actually the name of the pin on the Tegra package? I don't see
> anything like that the board schematic I have.
>

Well, there's more than one pin affected by this register. They're named:

DSI_B_CLK_P
DSI_B_CLK_N
DSI_B_D0_P
DSI_B_D0_N
DSI_B_D1_P
DSI_B_D1_N
DSI_B_D2_P
DSI_B_D2_N
DSI_B_D3_P
DSI_B_D3_N

I'll change this to TEGRA_PIN_DSI_B, does that work for you?


>
>>   #define DRV_PINGROUP_REG_A            0x868   /* bank 0 */
>>   #define PINGROUP_REG_A                        0x3000  /* bank 1 */
>> +#define APB_MISC_PINGROUP_REG_A                0x820   /* bank 2 */
>
>
> In order for that to work, an extra reg entry will be required in DT so that
> registers in bank 2 can be accessed. I would expect this patch (or series)
> to contain an addition to
> Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt to
> mention this. I assume you'll send a patch to
> arch/arm/boot/dts/tegra124.dtsi separately to add that entry.
>

Yep, sounds good.

>
>> +#define APB_MISC_PINGROUP(pg_name, r, b, f0, f1, f_safe)               \
>
>
> f_safe isn't present in any of the upstream Tegra pinctrl drivers any more,
> so that parameter isn't needed any more...
>
>
>> +       {                                                               \
>> +               .name = #pg_name,                                       \
>> +               .pins = pg_name##_pins,                                 \
>> +               .npins = ARRAY_SIZE(pg_name##_pins),                    \
>> +               .funcs = {                                              \
>> +                       TEGRA_MUX_ ## f0,                               \
>> +                       TEGRA_MUX_ ## f1,                               \
>> +               },                                                      \
>> +               .func_safe = TEGRA_MUX_ ## f_safe,                      \
>
>
> ... and I don't think that line will even compile, since that field doesn't
> exist?
>

Oh my, sorry about that. I mustn't have had my config set up correctly
when I built this.

> All 4 entries in .funcs[] should be initialized too. If two don't make
> sense, then they should at least be hard-coded to TEGRA_MUX_RSVD3/4. It
> would be nice if the driver knew that this pin only had two valid mux
> options, but I suppose updating the code to handle that special case isn't
> really worth it.
>
>
>>         DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,
>> 28,  2,  30,  2,  Y),
>> +
>> +       /*                      pg_name,        r       b       f0,
>> f1,     f_safe */
>> +       APB_MISC_PINGROUP(      csi_dsib,       0x820,  1,      CSI,
>> DSIB,   DSIB)
>>   };
>
>
> Can you make the indentation of the added lines consistent here. The
> existing code uses a TAB at the start of the line (but the patch uses
> spaces), and spaces internally (but the patch uses TABs) so columns don't
> have to waste space being TAB aligned. The pg_name column should be nestled
> right against the opening (, without any intervening space.

I'll upload a new version shortly.

Sean

Re: [PATCH] pinctrl: tegra: Add APB misc MIPI pad control

[Stephen Warren]

On 09/03/2014 09:24 AM, Sean Paul wrote:
> On Tue, Sep 2, 2014 at 4:31 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 09/02/2014 11:18 AM, Sean Paul wrote:
>>>
>>> This patch adds MIPI CSI/DSIB pad control mux register
>>> from the APB misc block to tegra pinctrl.
>>>
>>> Without writing to this register, the dsib pads are
>>> muxed as csi, and cannot be used.
>>>
>>> The register is not yet documented in the TRM, here is
>>> the description:
>>>
>>> 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
>>>          [31:02] RESERVED
>>>          [01:01] DSIB_MODE       [CSI=0,DSIB=1]
>>>          [00:00] RESERVED

>>> diff --git a/drivers/pinctrl/pinctrl-tegra124.c
>>> b/drivers/pinctrl/pinctrl-tegra124.c
>>
>>
>>> +#define TEGRA_PIN_CSI_DSIB                     _PIN(8)
>>
>>
>> Is that actually the name of the pin on the Tegra package? I don't see
>> anything like that the board schematic I have.
>
> Well, there's more than one pin affected by this register. They're named:
>
> DSI_B_CLK_P
> DSI_B_CLK_N
> DSI_B_D0_P
> DSI_B_D0_N
> DSI_B_D1_P
> DSI_B_D1_N
> DSI_B_D2_P
> DSI_B_D2_N
> DSI_B_D3_P
> DSI_B_D3_N
>
> I'll change this to TEGRA_PIN_DSI_B, does that work for you?

Would it be possible to add a pin entry for each individual pin, and 
then create a DSI_B group that contains all those pins? Mux selections 
are made on pin groups rather than individual pins, so this shouldn't 
affect anything except for a few data tables in the patch. This way, it 
keeps the PIN macros purely as pins, rather than sometimes using them 
for groups of pins. As background: On Tegra30+, there's a 1:1 mapping 
between pins and groups for the regular pinmux registers, but if you 
look at the Tegra20 HW/driver, you'll see a much smaller set of groups 
than pins there.

Re: [PATCH] pinctrl: tegra: Add APB misc MIPI pad control

[Sean Paul]

On Wed, Sep 3, 2014 at 11:34 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 09/03/2014 09:24 AM, Sean Paul wrote:
>>
>> On Tue, Sep 2, 2014 at 4:31 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
>> wrote:
>>>
>>> On 09/02/2014 11:18 AM, Sean Paul wrote:
>>>>
>>>>
>>>> This patch adds MIPI CSI/DSIB pad control mux register
>>>> from the APB misc block to tegra pinctrl.
>>>>
>>>> Without writing to this register, the dsib pads are
>>>> muxed as csi, and cannot be used.
>>>>
>>>> The register is not yet documented in the TRM, here is
>>>> the description:
>>>>
>>>> 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
>>>>          [31:02] RESERVED
>>>>          [01:01] DSIB_MODE       [CSI=0,DSIB=1]
>>>>          [00:00] RESERVED
>
>
>>>> diff --git a/drivers/pinctrl/pinctrl-tegra124.c
>>>> b/drivers/pinctrl/pinctrl-tegra124.c
>>>
>>>
>>>
>>>> +#define TEGRA_PIN_CSI_DSIB                     _PIN(8)
>>>
>>>
>>>
>>> Is that actually the name of the pin on the Tegra package? I don't see
>>> anything like that the board schematic I have.
>>
>>
>> Well, there's more than one pin affected by this register. They're named:
>>
>> DSI_B_CLK_P
>> DSI_B_CLK_N
>> DSI_B_D0_P
>> DSI_B_D0_N
>> DSI_B_D1_P
>> DSI_B_D1_N
>> DSI_B_D2_P
>> DSI_B_D2_N
>> DSI_B_D3_P
>> DSI_B_D3_N
>>
>> I'll change this to TEGRA_PIN_DSI_B, does that work for you?
>
>
> Would it be possible to add a pin entry for each individual pin, and then
> create a DSI_B group that contains all those pins?

Sure, sounds good to me.

Sean

> Mux selections are made
> on pin groups rather than individual pins, so this shouldn't affect anything
> except for a few data tables in the patch. This way, it keeps the PIN macros
> purely as pins, rather than sometimes using them for groups of pins. As
> background: On Tegra30+, there's a 1:1 mapping between pins and groups for
> the regular pinmux registers, but if you look at the Tegra20 HW/driver,
> you'll see a much smaller set of groups than pins there.

[PATCH v2 1/2] pinctrl: tegra: Add APB misc MIPI pad control

[Sean Paul]

This patch adds MIPI CSI/DSIB pad control mux register
from the APB misc block to tegra pinctrl.

Without writing to this register, the dsib pads are
muxed as csi, and cannot be used.

The register is not yet documented in the TRM, here is
the description:

70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
	[31:02] RESERVED
	[01:01] DSIB_MODE       [CSI=0,DSIB=1]
	[00:00] RESERVED

Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---

Changes in v2:
	- Added devicetree binding documentation
	- Added discrete pins for all pads, grouped in apb_dsi_b group
	- Changed group naming to be consistent with the other groups
	- Fixed compilation errors
	- Fixed indentation in tegra124_groups

 .../bindings/pinctrl/nvidia,tegra124-pinmux.txt    | 13 ++++-
 drivers/pinctrl/pinctrl-tegra124.c                 | 67 ++++++++++++++++++++++
 2 files changed, 77 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
index 6464bf7..5823feb 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
@@ -91,6 +91,12 @@ Valid values for pin and group names are:
     dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
     gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
 
+  apb groups:
+
+    These do not support any of the optional properties.
+
+    dsi_b
+
 Valid values for nvidia,functions are:
 
   blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
@@ -101,14 +107,15 @@ Valid values for nvidia,functions are:
   sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
   uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
   vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
-  dp, rtck, sys, clk tmds.
+  dp, rtck, sys, clk tmds. csi, dsi_b
 
 Example:
 
 	pinmux: pinmux {
 		compatible = "nvidia,tegra124-pinmux";
-		reg = <0x70000868 0x164		/* Pad control registers */
-		       0x70003000 0x434>;	/* PinMux registers */
+		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
+		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+		      <0x0 0x70000820 0x0 0x8>;   /* APB misc registers */
 	};
 
 Example pinmux entries:
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index e80797e..7137a0a 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -224,6 +224,16 @@
 #define TEGRA_PIN_OWR				_PIN(5)
 #define TEGRA_PIN_CLK_32K_IN			_PIN(6)
 #define TEGRA_PIN_JTAG_RTCK			_PIN(7)
+#define TEGRA_PIN_DSI_B_CLK_P			_PIN(8)
+#define TEGRA_PIN_DSI_B_CLK_N			_PIN(9)
+#define TEGRA_PIN_DSI_B_D0_P			_PIN(10)
+#define TEGRA_PIN_DSI_B_D0_N			_PIN(11)
+#define TEGRA_PIN_DSI_B_D1_P			_PIN(12)
+#define TEGRA_PIN_DSI_B_D1_N			_PIN(13)
+#define TEGRA_PIN_DSI_B_D2_P			_PIN(14)
+#define TEGRA_PIN_DSI_B_D2_N			_PIN(15)
+#define TEGRA_PIN_DSI_B_D3_P			_PIN(16)
+#define TEGRA_PIN_DSI_B_D3_N			_PIN(17)
 
 static const struct pinctrl_pin_desc tegra124_pins[] = {
 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
@@ -417,6 +427,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
 	PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 	PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
 };
 
 static const unsigned clk_32k_out_pa0_pins[] = {
@@ -1495,6 +1515,19 @@ static const unsigned drive_ao4_pins[] = {
 	TEGRA_PIN_JTAG_RTCK,
 };
 
+static const unsigned apb_dsi_b_pins[] = {
+	TEGRA_PIN_DSI_B_CLK_P,
+	TEGRA_PIN_DSI_B_CLK_N,
+	TEGRA_PIN_DSI_B_D0_P,
+	TEGRA_PIN_DSI_B_D0_N,
+	TEGRA_PIN_DSI_B_D1_P,
+	TEGRA_PIN_DSI_B_D1_N,
+	TEGRA_PIN_DSI_B_D2_P,
+	TEGRA_PIN_DSI_B_D2_N,
+	TEGRA_PIN_DSI_B_D3_P,
+	TEGRA_PIN_DSI_B_D3_N,
+};
+
 enum tegra_mux {
 	TEGRA_MUX_BLINK,
 	TEGRA_MUX_CCLA,
@@ -1580,6 +1613,8 @@ enum tegra_mux {
 	TEGRA_MUX_VI_ALT3,
 	TEGRA_MUX_VIMCLK2,
 	TEGRA_MUX_VIMCLK2_ALT,
+	TEGRA_MUX_CSI,
+	TEGRA_MUX_DSI_B,
 };
 
 #define FUNCTION(fname)					\
@@ -1672,10 +1707,13 @@ static struct tegra_function tegra124_functions[] = {
 	FUNCTION(vi_alt3),
 	FUNCTION(vimclk2),
 	FUNCTION(vimclk2_alt),
+	FUNCTION(csi),
+	FUNCTION(dsi_b),
 };
 
 #define DRV_PINGROUP_REG_A		0x868	/* bank 0 */
 #define PINGROUP_REG_A			0x3000	/* bank 1 */
+#define APB_MISC_PINGROUP_REG_A		0x820	/* bank 2 */
 
 #define PINGROUP_REG(r)			((r) - PINGROUP_REG_A)
 
@@ -1744,6 +1782,32 @@ static struct tegra_function tegra124_functions[] = {
 		.drvtype_bit = PINGROUP_BIT_##drvtype(6),		\
 	}
 
+#define APB_MISC_PINGROUP_REG_Y(r)	((r) - APB_MISC_PINGROUP_REG_A)
+
+#define APB_MISC_PINGROUP(pg_name, r, b, f0, f1)			\
+	{								\
+		.name = "apb_" #pg_name,				\
+		.pins = apb_##pg_name##_pins,				\
+		.npins = ARRAY_SIZE(apb_##pg_name##_pins),		\
+		.funcs = {						\
+			TEGRA_MUX_ ## f0,				\
+			TEGRA_MUX_ ## f1,				\
+			TEGRA_MUX_RSVD3,				\
+			TEGRA_MUX_RSVD4,				\
+		},							\
+		.mux_reg = APB_MISC_PINGROUP_REG_Y(r),			\
+		.mux_bank = 2,						\
+		.mux_bit = b,						\
+		.pupd_reg = -1,						\
+		.tri_reg = -1,						\
+		.einput_bit = -1,					\
+		.odrain_bit = -1,					\
+		.lock_bit = -1,						\
+		.ioreset_bit = -1,					\
+		.rcv_sel_bit = -1,					\
+		.drv_reg = -1,						\
+	}
+
 static const struct tegra_pingroup tegra124_groups[] = {
 	/*       pg_name,                f0,         f1,         f2,           f3,          r,      od, ior, rcv_sel */
 	PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        0x3000, N,   N,  N),
@@ -1979,6 +2043,9 @@ static const struct tegra_pingroup tegra124_groups[] = {
 	DRV_PINGROUP(hv0,         0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
 	DRV_PINGROUP(sdio4,       0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
 	DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
+
+	/*		  pg_name,   r      b  f0,  f1 */
+	APB_MISC_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B)
 };
 
 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
-- 
2.0.0

[PATCH 2/2] arm: dts: tegra124: Add APB_MISC_GP as a pinctrl bank

[Sean Paul]

This patch adds the APB_MISC_GP_MIPI_PAD_CTRL_0 as a pinctrl
bank so the new apb group can be muxed between CSI and DSI_B.

Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
 arch/arm/boot/dts/tegra124.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 03916ef..75b919f 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -204,7 +204,8 @@
 	pinmux: pinmux@0,70000868 {
 		compatible = "nvidia,tegra124-pinmux";
 		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
-		      <0x0 0x70003000 0x0 0x434>; /* Mux registers */
+		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+		      <0x0 0x70000820 0x0 0x8>;   /* APB misc registers */
 	};
 
 	/*
-- 
2.0.0

Re: [PATCH 2/2] arm: dts: tegra124: Add APB_MISC_GP as a pinctrl bank

[Stephen Warren]

On 09/03/2014 11:06 AM, Sean Paul wrote:
> This patch adds the APB_MISC_GP_MIPI_PAD_CTRL_0 as a pinctrl
> bank so the new apb group can be muxed between CSI and DSI_B.

> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi

>   	pinmux: pinmux@0,70000868 {
>   		compatible = "nvidia,tegra124-pinmux";
>   		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
> -		      <0x0 0x70003000 0x0 0x434>; /* Mux registers */
> +		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
> +		      <0x0 0x70000820 0x0 0x8>;   /* APB misc registers */

Same naming comment here as for the example in the DT binding docs.

Re: [PATCH v2 1/2] pinctrl: tegra: Add APB misc MIPI pad control

[Stephen Warren]

On 09/03/2014 11:06 AM, Sean Paul wrote:
> This patch adds MIPI CSI/DSIB pad control mux register
> from the APB misc block to tegra pinctrl.
>
> Without writing to this register, the dsib pads are
> muxed as csi, and cannot be used.
>
> The register is not yet documented in the TRM, here is
> the description:
>
> 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
> 	[31:02] RESERVED
> 	[01:01] DSIB_MODE       [CSI=0,DSIB=1]
> 	[00:00] RESERVED

> diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt

The definition of the reg property also needs to be extended. I would 
suggest:

  - reg: Should contain a list of base address and size pairs for:
      -- first entry - the drive strength and pad control registers.
      -- second entry - the pinmux registers
+    -- third entry - the MIPI_PAD_CTRL register

>       dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
>       gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
>
> +  apb groups:
> +
> +    These do not support any of the optional properties.
> +
> +    dsi_b

I don't think the term "optional properties" is quite right here; even 
the mux function property is optional. A better description might be:

+  MIPI groups:
+
+    These support only the nvidia,function property.
+
+    dsi_b

> +
>   Valid values for nvidia,functions are:
>
>     blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
> @@ -101,14 +107,15 @@ Valid values for nvidia,functions are:
>     sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
>     uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
>     vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
> -  dp, rtck, sys, clk tmds.
> +  dp, rtck, sys, clk tmds. csi, dsi_b

------>                    ^^ change to a comma

>   Example:
>
>   	pinmux: pinmux {
>   		compatible = "nvidia,tegra124-pinmux";
> -		reg = <0x70000868 0x164		/* Pad control registers */
> -		       0x70003000 0x434>;	/* PinMux registers */
> +		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
> +		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
> +		      <0x0 0x70000820 0x0 0x8>;   /* APB misc registers */

I think say "MIPI pad control" or "MIPI PAD CTRL" for the added line; 
all of the registers used by pinctrl are APB misc registers.

> diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c

>   #define DRV_PINGROUP_REG_A		0x868	/* bank 0 */
>   #define PINGROUP_REG_A			0x3000	/* bank 1 */
> +#define APB_MISC_PINGROUP_REG_A		0x820	/* bank 2 */

Oh, I think for the same reasons I mentioned above in the documentation, 
name that MIPI_PAD_CTRL_PINGROUP_REG_A?

> +#define APB_MISC_PINGROUP_REG_Y(r)	((r) - APB_MISC_PINGROUP_REG_A)
> +
> +#define APB_MISC_PINGROUP(pg_name, r, b, f0, f1)			\

... and those MIPI_PAD_CTRL_PINGROUP{,_REG_Y}

Sorry for not thinking about the naming issues in the .c file the last 
time around.

[PATCH v3 1/2] pinctrl: tegra: Add MIPI pad control

[Sean Paul]

This patch adds MIPI CSI/DSIB pad control mux register
from the APB misc block to tegra pinctrl.

Without writing to this register, the dsib pads are
muxed as csi, and cannot be used.

The register is not yet documented in the TRM, here is
the description:

70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
	[31:02] RESERVED
	[01:01] DSIB_MODE       [CSI=0,DSIB=1]
	[00:00] RESERVED

Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---

Changes in v2:
        - Added devicetree binding documentation
	- Added discrete pins for all pads, grouped in apb_dsi_b group
	- Changed group naming to be consistent with the other groups
	- Fixed compilation errors
	- Fixed indentation in tegra124_groups

Changes in v3:
	- Renamed group to mipi pad ctrl

 .../bindings/pinctrl/nvidia,tegra124-pinmux.txt    | 14 ++++-
 drivers/pinctrl/pinctrl-tegra124.c                 | 67 ++++++++++++++++++++++
 2 files changed, 78 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
index 6464bf7..189814e 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
@@ -10,6 +10,7 @@ Required properties:
 - reg: Should contain a list of base address and size pairs for:
     -- first entry - the drive strength and pad control registers.
     -- second entry - the pinmux registers
+    -- third entry - the MIPI_PAD_CTRL register
 
 Tegra124 adds the following optional properties for pin configuration subnodes.
 The macros for options are defined in the
@@ -91,6 +92,12 @@ Valid values for pin and group names are:
     dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
     gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
 
+  MIPI pad control groups:
+
+    These support only the nvidia,function property.
+
+    dsi_b
+
 Valid values for nvidia,functions are:
 
   blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
@@ -101,14 +108,15 @@ Valid values for nvidia,functions are:
   sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
   uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
   vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
-  dp, rtck, sys, clk tmds.
+  dp, rtck, sys, clk tmds, csi, dsi_b
 
 Example:
 
 	pinmux: pinmux {
 		compatible = "nvidia,tegra124-pinmux";
-		reg = <0x70000868 0x164		/* Pad control registers */
-		       0x70003000 0x434>;	/* PinMux registers */
+		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
+		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+		      <0x0 0x70000820 0x0 0x8>;   /* MIPI pad control */
 	};
 
 Example pinmux entries:
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index e80797e..287d374c 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -224,6 +224,16 @@
 #define TEGRA_PIN_OWR				_PIN(5)
 #define TEGRA_PIN_CLK_32K_IN			_PIN(6)
 #define TEGRA_PIN_JTAG_RTCK			_PIN(7)
+#define TEGRA_PIN_DSI_B_CLK_P			_PIN(8)
+#define TEGRA_PIN_DSI_B_CLK_N			_PIN(9)
+#define TEGRA_PIN_DSI_B_D0_P			_PIN(10)
+#define TEGRA_PIN_DSI_B_D0_N			_PIN(11)
+#define TEGRA_PIN_DSI_B_D1_P			_PIN(12)
+#define TEGRA_PIN_DSI_B_D1_N			_PIN(13)
+#define TEGRA_PIN_DSI_B_D2_P			_PIN(14)
+#define TEGRA_PIN_DSI_B_D2_N			_PIN(15)
+#define TEGRA_PIN_DSI_B_D3_P			_PIN(16)
+#define TEGRA_PIN_DSI_B_D3_N			_PIN(17)
 
 static const struct pinctrl_pin_desc tegra124_pins[] = {
 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
@@ -417,6 +427,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
 	PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 	PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
+	PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
 };
 
 static const unsigned clk_32k_out_pa0_pins[] = {
@@ -1495,6 +1515,19 @@ static const unsigned drive_ao4_pins[] = {
 	TEGRA_PIN_JTAG_RTCK,
 };
 
+static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
+	TEGRA_PIN_DSI_B_CLK_P,
+	TEGRA_PIN_DSI_B_CLK_N,
+	TEGRA_PIN_DSI_B_D0_P,
+	TEGRA_PIN_DSI_B_D0_N,
+	TEGRA_PIN_DSI_B_D1_P,
+	TEGRA_PIN_DSI_B_D1_N,
+	TEGRA_PIN_DSI_B_D2_P,
+	TEGRA_PIN_DSI_B_D2_N,
+	TEGRA_PIN_DSI_B_D3_P,
+	TEGRA_PIN_DSI_B_D3_N,
+};
+
 enum tegra_mux {
 	TEGRA_MUX_BLINK,
 	TEGRA_MUX_CCLA,
@@ -1580,6 +1613,8 @@ enum tegra_mux {
 	TEGRA_MUX_VI_ALT3,
 	TEGRA_MUX_VIMCLK2,
 	TEGRA_MUX_VIMCLK2_ALT,
+	TEGRA_MUX_CSI,
+	TEGRA_MUX_DSI_B,
 };
 
 #define FUNCTION(fname)					\
@@ -1672,10 +1707,13 @@ static struct tegra_function tegra124_functions[] = {
 	FUNCTION(vi_alt3),
 	FUNCTION(vimclk2),
 	FUNCTION(vimclk2_alt),
+	FUNCTION(csi),
+	FUNCTION(dsi_b),
 };
 
 #define DRV_PINGROUP_REG_A		0x868	/* bank 0 */
 #define PINGROUP_REG_A			0x3000	/* bank 1 */
+#define MIPI_PAD_CTRL_PINGROUP_REG_A	0x820	/* bank 2 */
 
 #define PINGROUP_REG(r)			((r) - PINGROUP_REG_A)
 
@@ -1744,6 +1782,32 @@ static struct tegra_function tegra124_functions[] = {
 		.drvtype_bit = PINGROUP_BIT_##drvtype(6),		\
 	}
 
+#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r)	((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
+
+#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1)			\
+	{								\
+		.name = "mipi_pad_ctrl_" #pg_name,			\
+		.pins = mipi_pad_ctrl_##pg_name##_pins,			\
+		.npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins),	\
+		.funcs = {						\
+			TEGRA_MUX_ ## f0,				\
+			TEGRA_MUX_ ## f1,				\
+			TEGRA_MUX_RSVD3,				\
+			TEGRA_MUX_RSVD4,				\
+		},							\
+		.mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r),		\
+		.mux_bank = 2,						\
+		.mux_bit = b,						\
+		.pupd_reg = -1,						\
+		.tri_reg = -1,						\
+		.einput_bit = -1,					\
+		.odrain_bit = -1,					\
+		.lock_bit = -1,						\
+		.ioreset_bit = -1,					\
+		.rcv_sel_bit = -1,					\
+		.drv_reg = -1,						\
+	}
+
 static const struct tegra_pingroup tegra124_groups[] = {
 	/*       pg_name,                f0,         f1,         f2,           f3,          r,      od, ior, rcv_sel */
 	PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        0x3000, N,   N,  N),
@@ -1979,6 +2043,9 @@ static const struct tegra_pingroup tegra124_groups[] = {
 	DRV_PINGROUP(hv0,         0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
 	DRV_PINGROUP(sdio4,       0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
 	DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
+
+	/*		       pg_name, r      b  f0,  f1 */
+	MIPI_PAD_CTRL_PINGROUP(dsi_b,   0x820, 1, CSI, DSI_B)
 };
 
 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
-- 
2.0.0

[PATCH v3 2/2] arm: dts: tegra124: Add APB_MISC_GP as a mipi pad control bank

[Sean Paul]

This patch adds the APB_MISC_GP_MIPI_PAD_CTRL_0 as a pinctrl
bank so the new mipi pad control group can be muxed between CSI
and DSI_B.

Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v2:
	- Added patch

Changes in v3:
	- Changed comment

 arch/arm/boot/dts/tegra124.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 03916ef..33660e8 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -204,7 +204,8 @@
 	pinmux: pinmux@0,70000868 {
 		compatible = "nvidia,tegra124-pinmux";
 		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
-		      <0x0 0x70003000 0x0 0x434>; /* Mux registers */
+		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+		      <0x0 0x70000820 0x0 0x8>;   /* MIPI pad control */
 	};
 
 	/*
-- 
2.0.0

Re: [PATCH v3 2/2] arm: dts: tegra124: Add APB_MISC_GP as a mipi pad control bank

[Thierry Reding]

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On Tue, Sep 09, 2014 at 03:58:46PM -0400, Sean Paul wrote:
> This patch adds the APB_MISC_GP_MIPI_PAD_CTRL_0 as a pinctrl
> bank so the new mipi pad control group can be muxed between CSI
> and DSI_B.
> 
> Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> Changes in v2:
> 	- Added patch
> 
> Changes in v3:
> 	- Changed comment
> 
>  arch/arm/boot/dts/tegra124.dtsi | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Applied to the for-3.19/dt branch.

Thierry

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Re: [PATCH v3 1/2] pinctrl: tegra: Add MIPI pad control

[Stephen Warren]

On 09/09/2014 01:58 PM, Sean Paul wrote:
> This patch adds MIPI CSI/DSIB pad control mux register
> from the APB misc block to tegra pinctrl.
>
> Without writing to this register, the dsib pads are
> muxed as csi, and cannot be used.
>
> The register is not yet documented in the TRM, here is
> the description:
>
> 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
> 	[31:02] RESERVED
> 	[01:01] DSIB_MODE       [CSI=0,DSIB=1]
> 	[00:00] RESERVED

These two patches look good to me.

I think we need to take both patches through the Tegra tree, since if 
the Tegra DTs start referencing the new pingroup, the driver must 
already know about it or it'll error out. So, I hope for an ack from Linus.

Of course, this only applies if you're sending patches to board .dts 
files to use the new feature for 3.18; if not, we can apply the pinctrl 
driver through the pinctrl tree instead, and wait until 3.19 to use the 
new pingroup. I assume you'll want to use the new feature soon though:-)

Re: [PATCH v3 1/2] pinctrl: tegra: Add MIPI pad control

[Sean Paul]

On Wed, Sep 10, 2014 at 12:08 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 09/09/2014 01:58 PM, Sean Paul wrote:
>>
>> This patch adds MIPI CSI/DSIB pad control mux register
>> from the APB misc block to tegra pinctrl.
>>
>> Without writing to this register, the dsib pads are
>> muxed as csi, and cannot be used.
>>
>> The register is not yet documented in the TRM, here is
>> the description:
>>
>> 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
>>         [31:02] RESERVED
>>         [01:01] DSIB_MODE       [CSI=0,DSIB=1]
>>         [00:00] RESERVED
>
>
> These two patches look good to me.
>
> I think we need to take both patches through the Tegra tree, since if the
> Tegra DTs start referencing the new pingroup, the driver must already know
> about it or it'll error out. So, I hope for an ack from Linus.
>
> Of course, this only applies if you're sending patches to board .dts files
> to use the new feature for 3.18; if not, we can apply the pinctrl driver
> through the pinctrl tree instead, and wait until 3.19 to use the new
> pingroup. I assume you'll want to use the new feature soon though:-)

I don't have any board .dts patches ready for upstream consumption
quite yet. Feel free to use whichever path to mainline you see fit.

Sean

Re: [PATCH v3 1/2] pinctrl: tegra: Add MIPI pad control

[Stephen Warren]

On 09/18/2014 12:56 PM, Sean Paul wrote:
> On Wed, Sep 10, 2014 at 12:08 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 09/09/2014 01:58 PM, Sean Paul wrote:
>>>
>>> This patch adds MIPI CSI/DSIB pad control mux register
>>> from the APB misc block to tegra pinctrl.
>>>
>>> Without writing to this register, the dsib pads are
>>> muxed as csi, and cannot be used.
>>>
>>> The register is not yet documented in the TRM, here is
>>> the description:
>>>
>>> 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
>>>          [31:02] RESERVED
>>>          [01:01] DSIB_MODE       [CSI=0,DSIB=1]
>>>          [00:00] RESERVED
>>
>>
>> These two patches look good to me.
>>
>> I think we need to take both patches through the Tegra tree, since if the
>> Tegra DTs start referencing the new pingroup, the driver must already know
>> about it or it'll error out. So, I hope for an ack from Linus.
>>
>> Of course, this only applies if you're sending patches to board .dts files
>> to use the new feature for 3.18; if not, we can apply the pinctrl driver
>> through the pinctrl tree instead, and wait until 3.19 to use the new
>> pingroup. I assume you'll want to use the new feature soon though:-)
>
> I don't have any board .dts patches ready for upstream consumption
> quite yet. Feel free to use whichever path to mainline you see fit.

I've actually just sent the Tegra pull requests for 3.18 today. Linus, 
if you want to take this whole series (or at least patch 1/2) through 
the pinctrl tree, that would be great. The patches will then already be 
there when we need them as a basis for any DT patches in the Tegra tree 
for 3.19.

Patch 2,
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Re: [PATCH v3 1/2] pinctrl: tegra: Add MIPI pad control

[Linus Walleij]

On Thu, Sep 18, 2014 at 12:42 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 09/18/2014 12:56 PM, Sean Paul wrote:

>> I don't have any board .dts patches ready for upstream consumption
>> quite yet. Feel free to use whichever path to mainline you see fit.
>
> I've actually just sent the Tegra pull requests for 3.18 today. Linus, if
> you want to take this whole series (or at least patch 1/2) through the
> pinctrl tree, that would be great.

I've applied patch 1/2 to the pinctrl tree

> The patches will then already be there
> when we need them as a basis for any DT patches in the Tegra tree for 3.19.
>
> Patch 2,
> Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

I prefer not to take DTS patches through pinctrl, I'll let this go through
the tegra tree next cycle.

But I take it that I can put your ACK on patch 1/2.

Yours,
Linus Walleij