From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?windows-1252?Q?Terje_Bergstr=F6m?= Subject: Re: [PATCH v4 05/12] memory: Add NVIDIA Tegra memory controller support Date: Thu, 30 Oct 2014 13:04:02 +0200 Message-ID: <54521B22.6070708@nvidia.com> References: <1413196434-5292-1-git-send-email-thierry.reding@gmail.com> <1413196434-5292-5-git-send-email-thierry.reding@gmail.com> <54520CFE.9060907@nvidia.com> <5452107D.8080207@nvidia.com> <54521181.8080005@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <54521181.8080005-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Alexandre Courbot , Thierry Reding , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Alexandre Courbot , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Stephen Warren List-Id: linux-tegra@vger.kernel.org On 30.10.2014 12:22, Alexandre Courbot wrote: > So should I understand that the GPU group is for addresses without bit > 34 set (hence forcibly disabled) while GPUB is used when that bit is > set? Or is it something else? That's exactly correct. And only GPUB can be programmed to be SMMU translated. Terje