[PATCH tegra-pinmux-scripts 1/2] fix kernel dt generation for Tegra 3

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* [PATCH tegra-pinmux-scripts 1/2] fix kernel dt generation for Tegra 3
@ 2015-01-05 21:47 Lucas Stach
       [not found] ` <1420494447-18510-1-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
  0 siblings, 1 reply; 4+ messages in thread
From: Lucas Stach @ 2015-01-05 21:47 UTC (permalink / raw)
  To: Stephen Warren; +Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA

There is no attribute rcv_sel on Tegra 3.

Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
---
 board-to-kernel-dt.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board-to-kernel-dt.py b/board-to-kernel-dt.py
index 86739db..20f27c3 100755
--- a/board-to-kernel-dt.py
+++ b/board-to-kernel-dt.py
@@ -56,7 +56,7 @@ for pincfg in board.pincfgs_by_num():
     print('				nvidia,enable-input = <' + mapper_bool(pincfg.e_inp) + '>;')
     if pincfg.gpio_pin.od:
         print('				nvidia,open-drain = <' + mapper_bool(pincfg.od) + '>;')
-    if pincfg.gpio_pin.rcv_sel:
+    if hasattr(pincfg.gpio_pin, 'rcv_sel') and pincfg.gpio_pin.rcv_sel:
         print('				nvidia,rcv-sel = <' + mapper_bool(pincfg.rcv_sel) + '>;')
     print('			};')
 
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 4+ messages in thread

[parent not found: <1420494447-18510-1-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>]

* [PATCH tegra-pinmux-scripts 2/2] add support for Beaver board
       [not found] ` <1420494447-18510-1-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
@ 2015-01-05 21:47   ` Lucas Stach
       [not found]     ` <1420494447-18510-2-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
  2015-01-05 22:07   ` [PATCH tegra-pinmux-scripts 1/2] fix kernel dt generation for Tegra 3 Stephen Warren
  1 sibling, 1 reply; 4+ messages in thread
From: Lucas Stach @ 2015-01-05 21:47 UTC (permalink / raw)
  To: Stephen Warren; +Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA

This leaves some pins unconfigured, but is all I could work out
from the existing U-Boot and Kernel code/DTs.

Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
---
 configs/beaver.board | 242 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 242 insertions(+)
 create mode 100644 configs/beaver.board

diff --git a/configs/beaver.board b/configs/beaver.board
new file mode 100644
index 0000000..ec3edc9
--- /dev/null
+++ b/configs/beaver.board
@@ -0,0 +1,242 @@
+soc = 'tegra30'
+
+pins = (
+    #pin,                      mux,            gpio_init, pull,   tri,   e_inp, od
+    ('sdmmc1_clk_pz0',         'sdmmc1',       None,      'none', False, True,  False),
+    ('sdmmc1_cmd_pz1',         'sdmmc1',       None,      'up',   False, True,  False),
+    ('sdmmc1_dat3_py4',        'sdmmc1',       None,      'up',   False, True,  False),
+    ('sdmmc1_dat2_py5',        'sdmmc1',       None,      'up',   False, True,  False),
+    ('sdmmc1_dat1_py6',        'sdmmc1',       None,      'up',   False, True,  False),
+    ('sdmmc1_dat0_py7',        'sdmmc1',       None,      'up',   False, True,  False),
+    ('sdmmc3_clk_pa6',         'sdmmc3',       None,      'none', False, True,  False),
+    ('sdmmc3_cmd_pa7',         'sdmmc3',       None,      'up',   False, True,  False),
+    ('sdmmc3_dat3_pb4',        'sdmmc3',       None,      'up',   False, True,  False),
+    ('sdmmc3_dat2_pb5',        'sdmmc3',       None,      'up',   False, True,  False),
+    ('sdmmc3_dat1_pb6',        'sdmmc3',       None,      'up',   False, True,  False),
+    ('sdmmc3_dat0_pb7',        'sdmmc3',       None,      'up',   False, True,  False),
+    ('sdmmc3_dat4_pd1',        'sdmmc3',       None,      'up',   False, True,  False),
+    ('sdmmc3_dat5_pd0',        'sdmmc3',       None,      'up',   False, True,  False),
+    ('sdmmc3_dat6_pd3',        'rsvd1',        None,      'none', False, True,  False),
+    ('sdmmc3_dat7_pd4',        'rsvd1',        None,      'none', False, True,  False),
+    ('sdmmc4_clk_pcc4',        'sdmmc4',       None,      'none', False, True,  False),
+    ('sdmmc4_cmd_pt7',         'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_dat0_paa0',       'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_dat1_paa1',       'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_dat2_paa2',       'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_dat3_paa3',       'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_dat4_paa4',       'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_dat5_paa5',       'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_dat6_paa6',       'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_dat7_paa7',       'sdmmc4',       None,      'up',   False, True,  False),
+    ('sdmmc4_rst_n_pcc3',      'sdmmc4',       None,      'down', False, True,  False),
+    ('gen1_i2c_scl_pc4',       'i2c1',         None,      'none', False, True,  True ),
+    ('gen1_i2c_sda_pc5',       'i2c1',         None,      'none', False, True,  True ),
+    ('gen2_i2c_scl_pt5',       'i2c2',         None,      'none', False, True,  True ),
+    ('gen2_i2c_sda_pt6',       'i2c2',         None,      'none', False, True,  True ),
+    ('cam_i2c_scl_pbb1',       'i2c3',         None,      'none', False, True,  True ),
+    ('cam_i2c_sda_pbb2',       'i2c3',         None,      'none', False, True,  True ),
+    ('ddc_scl_pv4',            'i2c4',         None,      'none', False, True,  True ),
+    ('ddc_sda_pv5',            'i2c4',         None,      'none', False, True,  True ),
+    ('pwr_i2c_scl_pz6',        'i2cpwr',       None,      'none', False, True,  True ),
+    ('pwr_i2c_sda_pz7',        'i2cpwr',       None,      'none', False, True,  True ),
+    ('ulpi_data0_po1',         'uarta',        None,      'none', False, False, False),
+    ('ulpi_data1_po2',         'uarta',        None,      'none', False, True,  False),
+    ('ulpi_data2_po3',         'uarta',        None,      'none', False, True,  False),
+    ('ulpi_data3_po4',         'rsvd1',        None,      'none', False, True,  False),
+    ('ulpi_data4_po5',         'uarta',        None,      'none', False, True,  False),
+    ('ulpi_data5_po6',         'uarta',        None,      'none', False, True,  False),
+    ('ulpi_data6_po7',         'uarta',        None,      'none', False, True,  False),
+    ('ulpi_data7_po0',         'uarta',        None,      'none', False, False, False),
+    ('ulpi_clk_py0',           'uartd',        None,      'none', False, False, False),
+    ('ulpi_dir_py1',           'uartd',        None,      'none', False, True,  False),
+    ('ulpi_nxt_py2',           'uartd',        None,      'none', False, True,  False),
+    ('ulpi_stp_py3',           'uartd',        None,      'none', False, False, False),
+    ('dap3_fs_pp0',            'i2s2',         None,      'none', False, True,  False),
+    ('dap3_din_pp1',           'i2s2',         None,      'none', False, True,  False),
+    ('dap3_dout_pp2',          'i2s2',         None,      'none', False, True,  False),
+    ('dap3_sclk_pp3',          'i2s2',         None,      'none', False, True,  False),
+    ('pv2',                    'owr',          None,      'none', False, False, False),
+    ('pv3',                    'rsvd1',        None,      'none', False, False, False),
+    ('clk2_out_pw5',           'extperiph2',   None,      'none', False, True,  False),
+    ('clk2_req_pcc5',          'dap',          None,      'none', False, True,  False),
+    ('lcd_pwr1_pc1',           'displaya',     None,      'none', False, True,  False),
+    ('lcd_pwr2_pc6',           'displaya',     None,      'none', False, True,  False),
+    ('lcd_sdin_pz2',           'displaya',     None,      'none', False, True,  False),
+    ('lcd_sdout_pn5',          'displaya',     None,      'none', False, True,  False),
+    ('lcd_wr_n_pz3',           'displaya',     None,      'none', False, True,  False),
+    ('lcd_cs0_n_pn4',          'displaya',     None,      'none', False, True,  False),
+    ('lcd_dc0_pn6',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_sck_pz4',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_pwr0_pb2',           'displaya',     None,      'none', False, True,  False),
+    ('lcd_pclk_pb3',           'displaya',     None,      'none', False, True,  False),
+    ('lcd_de_pj1',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_hsync_pj3',          'displaya',     None,      'none', False, True,  False),
+    ('lcd_vsync_pj4',          'displaya',     None,      'none', False, True,  False),
+    ('lcd_d0_pe0',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d1_pe1',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d2_pe2',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d3_pe3',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d4_pe4',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d5_pe5',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d6_pe6',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d7_pe7',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d8_pf0',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d9_pf1',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_d10_pf2',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d11_pf3',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d12_pf4',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d13_pf5',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d14_pf6',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d15_pf7',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d16_pm0',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d17_pm1',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d18_pm2',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d19_pm3',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d20_pm4',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d21_pm5',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d22_pm6',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_d23_pm7',            'displaya',     None,      'none', False, True,  False),
+    ('lcd_cs1_n_pw0',          'displaya',     None,      'none', False, True,  False),
+    ('lcd_m1_pw1',             'displaya',     None,      'none', False, True,  False),
+    ('lcd_dc1_pd2',            'displaya',     None,      'none', False, True,  False),
+    ('crt_hsync_pv6',          'crt',          None,      'none', False, False, False),
+    ('crt_vsync_pv7',          'crt',          None,      'none', False, False, False),
+    ('vi_d0_pt4',              'rsvd1',        None,      'none', False, True,  False),
+    ('vi_d1_pd5',              'sdmmc2',       None,      'none', False, True,  False),
+    ('vi_d2_pl0',              'sdmmc2',       None,      'none', False, True,  False),
+    ('vi_d3_pl1',              'sdmmc2',       None,      'none', False, True,  False),
+    ('vi_d4_pl2',              'vi',           None,      'none', False, False, False),
+    ('vi_d5_pl3',              'sdmmc2',       None,      'none', False, True,  False),
+    ('vi_d7_pl5',              'sdmmc2',       None,      'none', False, True,  False),
+    ('vi_d10_pt2',             'rsvd1',        None,      'none', False, True,  False),
+    ('vi_mclk_pt1',            'vi',           None,      'up',   False, True,  False),
+    ('uart2_rxd_pc3',          'uartb',        None,      'none', False, True,  False),
+    ('uart2_txd_pc2',          'uartb',        None,      'none', False, False, False),
+    ('uart2_rts_n_pj6',        'uartb',        None,      'none', False, False, False),
+    ('uart2_cts_n_pj5',        'uartb',        None,      'none', False, True,  False),
+    ('uart3_rxd_pw7',          'uartc',        None,      'none', False, True,  False),
+    ('uart3_txd_pw6',          'uartc',        None,      'none', False, False, False),
+    ('uart3_rts_n_pc0',        'uartc',        None,      'none', False, False, False),
+    ('uart3_cts_n_pa1',        'uartc',        None,      'none', False, True,  False),
+    ('pu0',                    'rsvd1',        None,      'none', False, True,  False),
+    ('pu1',                    'rsvd1',        None,      'none', False, False, False),
+    ('pu2',                    'rsvd1',        None,      'none', False, True,  False),
+    ('pu3',                    'rsvd1',        None,      'none', False, True,  False),
+    ('pu4',                    'pwm1',         None,      'none', False, False, False),
+    ('pu5',                    'pwm2',         None,      'none', False, False, False),
+    ('pu6',                    'rsvd1',        None,      'none', False, True,  False),
+    ('dap4_fs_pp4',            'i2s3',         None,      'none', False, True,  False),
+    ('dap4_din_pp5',           'i2s3',         None,      'none', False, True,  False),
+    ('dap4_dout_pp6',          'i2s3',         None,      'none', False, True,  False),
+    ('dap4_sclk_pp7',          'i2s3',         None,      'none', False, True,  False),
+    ('clk3_out_pee0',          'extperiph3',   None,      'none', False, False, False),
+    ('clk3_req_pee1',          'dev3',         None,      'none', False, True,  False),
+    ('gmi_wp_n_pc7',           'gmi',          None,      'none', False, True,  False),
+    ('gmi_cs2_n_pk3',          'rsvd1',        None,      'up',   False, True,  False),
+    ('gmi_ad8_ph0',            'pwm0',         None,      'none', False, False, False),
+    ('gmi_ad10_ph2',           'nand',         None,      'none', False, False, False),
+    ('gmi_a16_pj7',            'spi4',         None,      'none', False, True,  False),
+    ('gmi_a17_pb0',            'spi4',         None,      'none', False, True,  False),
+    ('gmi_a18_pb1',            'spi4',         None,      'none', False, True,  False),
+    ('gmi_a19_pk7',            'spi4',         None,      'none', False, True,  False),
+    ('cam_mclk_pcc0',          'vi_alt3',      None,      'up',   False, True,  False),
+    ('pcc1',                   'rsvd1',        None,      'none', False, True,  False),
+    ('pbb0',                   'rsvd1',        None,      'none', False, True,  False),
+    ('pbb3',                   'vgp3',         None,      'none', False, True,  False),
+    ('pbb5',                   'vgp5',         None,      'none', False, True,  False),
+    ('pbb6',                   'vgp6',         None,      'none', False, True,  False),
+    ('pbb7',                   'i2s4',         None,      'none', False, True,  False),
+    ('pcc2',                   'i2s4',         None,      'none', False, True,  False),
+    ('jtag_rtck_pu7',          'rtck',         None,      'none', False, False, False),
+    ('kb_row0_pr0',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row1_pr1',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row2_pr2',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row3_pr3',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row4_pr4',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row5_pr5',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row6_pr6',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row7_pr7',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row8_ps0',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row9_ps1',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_row10_ps2',           'kbc',          None,      'up',   False, True,  False),
+    ('kb_row11_ps3',           'kbc',          None,      'up',   False, True,  False),
+    ('kb_row12_ps4',           'kbc',          None,      'up',   False, True,  False),
+    ('kb_row13_ps5',           'kbc',          None,      'up',   False, True,  False),
+    ('kb_row14_ps6',           'kbc',          None,      'up',   False, True,  False),
+    ('kb_row15_ps7',           'kbc',          None,      'up',   False, True,  False),
+    ('kb_col0_pq0',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_col1_pq1',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_col2_pq2',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_col3_pq3',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_col4_pq4',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_col5_pq5',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_col6_pq6',            'kbc',          None,      'up',   False, True,  False),
+    ('kb_col7_pq7',            'kbc',          None,      'up',   False, True,  False),
+    ('pv0',                    'rsvd1',        None,      'up',   False, True,  False),
+    ('clk_32k_out_pa0',        'blink',        None,      'none', False, False, False),
+    ('sys_clk_req_pz5',        'sysclk',       None,      'none', False, False, False),
+    ('owr',                    'owr',          None,      'none', False, True,  False),
+    ('dap1_fs_pn0',            'i2s0',         None,      'none', False, True,  False),
+    ('dap1_din_pn1',           'i2s0',         None,      'none', False, True,  False),
+    ('dap1_dout_pn2',          'i2s0',         None,      'none', False, True,  False),
+    ('dap1_sclk_pn3',          'i2s0',         None,      'none', False, True,  False),
+    ('clk1_req_pee2',          'dap',          None,      'none', False, True,  False),
+    ('clk1_out_pw4',           'extperiph1',   None,      'none', False, True,  False),
+    ('spdif_in_pk6',           'spdif',        None,      'none', False, True,  False),
+    ('spdif_out_pk5',          'spdif',        None,      'none', False, False, False),
+    ('dap2_fs_pa2',            'i2s1',         None,      'none', False, True,  False),
+    ('dap2_din_pa4',           'i2s1',         None,      'none', False, True,  False),
+    ('dap2_dout_pa5',          'i2s1',         None,      'none', False, True,  False),
+    ('dap2_sclk_pa3',          'i2s1',         None,      'none', False, True,  False),
+    ('spi2_cs1_n_pw2',         'spi2',         None,      'up',   False, True,  False),
+    ('spi1_mosi_px4',          'spi1',         None,      'none', False, True,  False),
+    ('spi1_sck_px5',           'spi1',         None,      'none', False, True,  False),
+    ('spi1_cs0_n_px6',         'spi1',         None,      'none', False, True,  False),
+    ('spi1_miso_px7',          'spi1',         None,      'none', False, True,  False),
+    ('pex_l0_prsnt_n_pdd0',    'pcie',         None,      'none', False, True,  False),
+    ('pex_l0_rst_n_pdd1',      'pcie',         None,      'none', False, False, False),
+    ('pex_l0_clkreq_n_pdd2',   'pcie',         None,      'none', False, True,  False),
+    ('pex_wake_n_pdd3',        'pcie',         None,      'none', False, True,  False),
+    ('pex_l1_prsnt_n_pdd4',    'pcie',         None,      'up',   False, True,  False),
+    ('pex_l1_rst_n_pdd5',      'pcie',         None,      'none', False, False, False),
+    ('pex_l1_clkreq_n_pdd6',   'pcie',         None,      'up',   False, True,  False),
+    ('pex_l2_prsnt_n_pdd7',    'pcie',         None,      'none', False, True,  False),
+    ('pex_l2_rst_n_pcc6',      'pcie',         None,      'none', False, False, False),
+    ('pex_l2_clkreq_n_pcc7',   'pcie',         None,      'none', False, True,  False),
+    ('hdmi_cec_pee3',          'cec',          None,      'none', False, True,  False),
+    ('hdmi_int_pn7',           'rsvd1',        None,      'none', True,  True,  False),
+    ('gmi_iordy_pi5',          'rsvd1',        None,      'up',   False, True,  False),
+    ('vi_d11_pt3',             'rsvd1',        None,      'up',   False, True,  False),
+    ('gmi_ad12_ph4',           'nand',         None,      'up',   False, True,  False),
+    ('gmi_ad14_ph6',           'nand',         None,      'none', False, False, False),
+    ('spi2_sck_px2',           'gmi',          None,      'none', False, True,  False),
+    ('pbb4',                   'vgp4',         None,      'none', False, True,  False),
+    ('vi_d6_pl4',              'vi',           None,      'none', False, False, False),
+    ('vi_d8_pl6',              'sdmmc2',       None,      'none', False, True,  False),
+    ('vi_d9_pl7',              'sdmmc2',       None,      'none', False, True,  False),
+    ('vi_pclk_pt0',            'rsvd1',        None,      'up',   False, True,  False),
+    ('vi_hsync_pd7',           'rsvd1',        None,      'none', False, True,  False),
+    ('vi_vsync_pd6',           'rsvd1',        None,      'none', False, True,  False),
+    ('gmi_wait_pi7',           'nand',         None,      'up',   True,  False, False),
+    ('gmi_adv_n_pk0',          'nand',         None,      'none', True,  False, False),
+    ('gmi_clk_pk1',            'nand',         None,      'none', True,  False, False),
+    ('gmi_cs3_n_pk4',          'nand',         None,      'none', True,  False, False),
+    ('gmi_cs7_n_pi6',          'nand',         None,      'up',   True,  True,  False),
+    ('gmi_ad0_pg0',            'nand',         None,      'none', True,  False, False),
+    ('gmi_ad1_pg1',            'nand',         None,      'none', True,  False, False),
+    ('gmi_ad2_pg2',            'nand',         None,      'none', True,  False, False),
+    ('gmi_ad3_pg3',            'nand',         None,      'none', True,  False, False),
+    ('gmi_ad4_pg4',            'nand',         None,      'none', True,  False, False),
+    ('gmi_ad5_pg5',            'nand',         None,      'none', True,  False, False),
+    ('gmi_ad6_pg6',            'nand',         None,      'none', True,  False, False),
+    ('gmi_ad7_pg7',            'nand',         None,      'none', True,  False, False),
+    ('gmi_ad9_ph1',            'pwm1',         None,      'none', True,  False, False),
+    ('gmi_ad11_ph3',           'nand',         None,      'none', True,  False, False),
+    ('gmi_ad13_ph5',           'nand',         None,      'up',   True,  True,  False),
+    ('gmi_wr_n_pi0',           'nand',         None,      'none', True,  False, False),
+    ('gmi_oe_n_pi1',           'nand',         None,      'none', True,  False, False),
+    ('gmi_dqs_pi2',            'nand',         None,      'none', True,  False, False),
+)
+
+drive_groups = (
+)
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 4+ messages in thread

[parent not found: <1420494447-18510-2-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>]

* Re: [PATCH tegra-pinmux-scripts 2/2] add support for Beaver board
       [not found]     ` <1420494447-18510-2-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
@ 2015-01-09 17:16       ` Stephen Warren
  0 siblings, 0 replies; 4+ messages in thread
From: Stephen Warren @ 2015-01-09 17:16 UTC (permalink / raw)
  To: Lucas Stach; +Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA

On 01/05/2015 02:47 PM, Lucas Stach wrote:
> This leaves some pins unconfigured, but is all I could work out
> from the existing U-Boot and Kernel code/DTs.

I've applied the series. I added a note to the top of beaver.board:

> # Note that this data was reverse-engineered from current upstream SW; it is
> # not a complete error-checked NVIDIA-supplied data set. That doesn't mean
> # anything is wrong with the data, simply that it was not generated using the
> # normal flow for NVIDIA reference boards (auto-generation from spreadsheets
> # supplied by NVIDIA syseng).

I hope that's OK.

One thing that might be worth doing: Boot the system you have, test that 
everything works, then fill in all the missing pins/values based on the 
actual register settings in HW (and cross-check the others with what's 
already in this file). At least that would eliminate the warnings from 
./board-to-*.py re: some pins being unconfigured, without changing 
anything about the way the pinmux ends up being programmed.

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH tegra-pinmux-scripts 1/2] fix kernel dt generation for Tegra 3
       [not found] ` <1420494447-18510-1-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
  2015-01-05 21:47   ` [PATCH tegra-pinmux-scripts 2/2] add support for Beaver board Lucas Stach
@ 2015-01-05 22:07   ` Stephen Warren
  1 sibling, 0 replies; 4+ messages in thread
From: Stephen Warren @ 2015-01-05 22:07 UTC (permalink / raw)
  To: Lucas Stach; +Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA

On 01/05/2015 02:47 PM, Lucas Stach wrote:
> There is no attribute rcv_sel on Tegra 3.

> diff --git a/board-to-kernel-dt.py b/board-to-kernel-dt.py

> -    if pincfg.gpio_pin.rcv_sel:
> +    if hasattr(pincfg.gpio_pin, 'rcv_sel') and pincfg.gpio_pin.rcv_sel:

It might be slightly simpler to do:

if pincfg.gpio_pin.get('rcv_sel', false):

?

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2015-01-09 17:16 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-01-05 21:47 [PATCH tegra-pinmux-scripts 1/2] fix kernel dt generation for Tegra 3 Lucas Stach
     [not found] ` <1420494447-18510-1-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
2015-01-05 21:47   ` [PATCH tegra-pinmux-scripts 2/2] add support for Beaver board Lucas Stach
     [not found]     ` <1420494447-18510-2-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
2015-01-09 17:16       ` Stephen Warren
2015-01-05 22:07   ` [PATCH tegra-pinmux-scripts 1/2] fix kernel dt generation for Tegra 3 Stephen Warren

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