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From: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Peter De Schrijver
	<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	Mike Turquette
	<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Alexandre Courbot
	<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v4 01/20] clk: tegra: Modify tegra_audio_clk_init to accept more plls
Date: Thu, 7 May 2015 11:49:49 -0400	[thread overview]
Message-ID: <554B899D.5020902@nvidia.com> (raw)
In-Reply-To: <20150507151545.GB25866-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>

On 5/7/2015 11:15 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Mon, May 04, 2015 at 12:37:21PM -0400, Rhyland Klein wrote:
> [...]
>> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
>> index 8237d16b4075..0d67efb3dd6a 100644
>> --- a/drivers/clk/tegra/clk-tegra114.c
>> +++ b/drivers/clk/tegra/clk-tegra114.c
>> @@ -935,6 +935,10 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
>>  	[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
>>  };
>>  
>> +static struct tegra_audio_clk_info tegra114_audio_plls[] = {
>> +	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
>> +};
>> +
>>  static struct clk **clks;
>>  
>>  static unsigned long osc_freq;
>> @@ -1483,7 +1487,8 @@ static void __init tegra114_clock_init(struct device_node *np)
>>  	tegra114_fixed_clk_init(clk_base);
>>  	tegra114_pll_init(clk_base, pmc_base);
>>  	tegra114_periph_clk_init(clk_base, pmc_base);
>> -	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
>> +	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
>> +			     &tegra114_audio_plls, 1);
> 
> This throws a build warning, it should be tegra114_audio_plls (without
> the ampersand). Also I think you should use ARRAY_SIZE() instead of
> hard-coding the number of entries here.

I swear I had changed those without the ampersand ... But yah ARRAY_SIZE
makes much more sense. Will change throughout...

> 
>>  	tegra_pmc_clk_init(pmc_base, tegra114_clks);
>>  	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
>>  					&pll_x_params);
>> diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
>> index 11f857cd5f6a..169e236f3627 100644
>> --- a/drivers/clk/tegra/clk-tegra124.c
>> +++ b/drivers/clk/tegra/clk-tegra124.c
>> @@ -1413,6 +1413,10 @@ static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
>>  	{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
>>  };
>>  
>> +static struct tegra_audio_clk_info tegra124_audio_plls[] = {
>> +	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
>> +};
>> +
>>  /**
>>   * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
>>   *
>> @@ -1489,7 +1493,8 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
>>  	tegra_fixed_clk_init(tegra124_clks);
>>  	tegra124_pll_init(clk_base, pmc_base);
>>  	tegra124_periph_clk_init(clk_base, pmc_base);
>> -	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
>> +	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
>> +			     tegra124_audio_plls, 1);
> 
> ARRAY_SIZE() here as well. The ampersand isn't there in this case...
> 
>>  	tegra_pmc_clk_init(pmc_base, tegra124_clks);
>>  
>>  	/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
>> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
>> index 4b26509fc218..3198c7b7946c 100644
>> --- a/drivers/clk/tegra/clk-tegra30.c
>> +++ b/drivers/clk/tegra/clk-tegra30.c
>> @@ -1406,6 +1406,10 @@ static const struct of_device_id pmc_match[] __initconst = {
>>  	{},
>>  };
>>  
>> +static struct tegra_audio_clk_info tegra30_audio_plls[] = {
>> +	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
>> +};
>> +
>>  static void __init tegra30_clock_init(struct device_node *np)
>>  {
>>  	struct device_node *node;
>> @@ -1443,7 +1447,8 @@ static void __init tegra30_clock_init(struct device_node *np)
>>  	tegra30_pll_init();
>>  	tegra30_super_clk_init();
>>  	tegra30_periph_clk_init();
>> -	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);
>> +	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
>> +			     &tegra30_audio_plls, 1);
> 
> Same comments as for Tegra114.
> 
>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> [...]
>> @@ -607,7 +622,8 @@ void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
>>  
>>  void tegra_audio_clk_init(void __iomem *clk_base,
>>  			void __iomem *pmc_base, struct tegra_clk *tegra_clks,
>> -			struct tegra_clk_pll_params *pll_params);
>> +			struct tegra_audio_clk_info *audio_info,
>> +			int num_plls);
> 
> Oh, and make num_plls unsigned int, please.

Will do!

Thanks,
Rhyland

> 
> Thierry
> 
> * Unknown Key
> * 0x7F3EB3A1
> 


-- 
nvpublic

  parent reply	other threads:[~2015-05-07 15:49 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-04 16:37 [PATCH v4 00/20] Tegra210 Clock Support Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 05/20] clk: tegra: pll: update warning msg Rhyland Klein
     [not found]   ` <1430757460-9478-6-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 20:20     ` Benson Leung
     [not found] ` <1430757460-9478-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 16:37   ` [PATCH v4 01/20] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
     [not found]     ` <1430757460-9478-2-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 18:05       ` Benson Leung
2015-05-07 15:15       ` Thierry Reding
     [not found]         ` <20150507151545.GB25866-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2015-05-07 15:49           ` Rhyland Klein [this message]
2015-05-04 16:37   ` [PATCH v4 02/20] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
     [not found]     ` <1430757460-9478-3-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 19:45       ` Benson Leung
     [not found]         ` <CANLzEkuxPMX2+rq4EkCs6iV4=qRK69u=Ezgy4Zn_KsSh1+oEfA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-05 20:14           ` Rhyland Klein
2015-05-06 13:59             ` Thierry Reding
2015-05-06 16:24               ` Rhyland Klein
2015-05-04 21:19       ` Andrew Bresticker
2015-05-06 11:20     ` Jim Lin
2015-05-06 14:15       ` Thierry Reding
2015-05-06 16:20         ` Rhyland Klein
2015-05-06 14:12     ` Thierry Reding
2015-05-04 16:37   ` [PATCH v4 03/20] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-05-04 16:37   ` [PATCH v4 04/20] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-04 20:11     ` Benson Leung
2015-05-04 16:37   ` [PATCH v4 06/20] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
     [not found]     ` <1430757460-9478-7-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 20:35       ` Benson Leung
     [not found]         ` <CANLzEksajPjf1VH8Zn-1oXhgL8f-b7GuCBprExTP-w18WbCC4A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-06 14:18           ` Thierry Reding
2015-05-04 16:37   ` [PATCH v4 08/20] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
     [not found]     ` <1430757460-9478-9-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 23:01       ` Benson Leung
     [not found]         ` <CANLzEksFVpYOtcG5QHHfQa6bGXJ6nMYrsP4yG=5wszxCHrWqug-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-05 19:16           ` Rhyland Klein
2015-05-06 13:57             ` Thierry Reding
2015-05-06 16:16               ` Rhyland Klein
2015-05-04 16:37   ` [PATCH v4 09/20] clk: tegra: pll: Add logic for SS Rhyland Klein
     [not found]     ` <1430757460-9478-10-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 23:11       ` Benson Leung
2015-05-05 20:15         ` Rhyland Klein
2015-05-04 16:37   ` [PATCH v4 11/20] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-05 17:15     ` Benson Leung
2015-05-04 16:37   ` [PATCH v4 12/20] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
2015-05-07 15:11     ` Thierry Reding
2015-05-04 16:37   ` [PATCH v4 14/20] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-05-04 16:37   ` [PATCH v4 16/20] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-05-04 16:37   ` [PATCH v4 17/20] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-05-04 16:37   ` [PATCH v4 18/20] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-04 16:37   ` [PATCH v4 19/20] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-06 14:51     ` Thierry Reding
     [not found]       ` <20150506145113.GH22098-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2015-05-06 16:18         ` Rhyland Klein
2015-05-06 17:21         ` Rhyland Klein
     [not found]           ` <554A4D82.80307-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-07 15:16             ` Thierry Reding
2015-05-07 10:39     ` Jim Lin
     [not found]       ` <554B40D7.3040207-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-07 16:07         ` Rhyland Klein
2015-05-07 15:18     ` Thierry Reding
2015-05-05 13:14   ` [PATCH v4 00/20] Tegra210 Clock Support Thierry Reding
2015-05-05 15:55     ` Rhyland Klein
2015-05-06 13:37       ` Thierry Reding
2015-05-06 16:10         ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 07/20] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
     [not found]   ` <1430757460-9478-8-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 21:42     ` Benson Leung
2015-05-04 16:37 ` [PATCH v4 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
     [not found]   ` <1430757460-9478-11-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 23:34     ` Benson Leung
     [not found]       ` <CANLzEktX3tiBXvxKgToUr5S7xZ+YibpeG6tDvW1R=qkW6_T5WQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-05 19:55         ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 13/20] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 15/20] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 20/20] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein

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