From: Jim Lin <jilin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v5 20/21] clk: tegra210: add support for Tegra210 clocks
Date: Wed, 20 May 2015 17:47:22 +0800 [thread overview]
Message-ID: <555C582A.7050508@nvidia.com> (raw)
In-Reply-To: <1431451444-23155-22-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 05/13/2015 01:24 AM, Rhyland Klein wrote:
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> new file mode 100644
> index 000000000000..7f25e60e4d48
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-tegra210.c
>
> +
> +static struct tegra_clk_init_table common_init_table[] __initdata = {
> + {TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0},
> + {TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0},
> + {TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0},
> + {TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0},
> + {TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1},
> + {TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1},
> + {TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1},
> + {TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1},
> + {TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1},
> + {TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0},
> + {TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0},
> + {TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0},
> + {TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0},
> + {TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0},
> + {TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1},
> + {TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1},
> + {TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 1},
> + {TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1},
> + {TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1},
> + {TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1},
> + {TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 624000000, 0},
> + {TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 0},
> + {TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 0},
Could you help to modify this as the following?
Clocks have to be enabled only once.
+ {TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 624000000, 1},
+ {TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1},
+ {TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1},
> + {TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0},
> + {TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0},
> + {TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_PLL_U_60M, 60000000, 0},
> + {TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_RE_OUT, 224000000, 0},
> + {TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_RE_OUT, 112000000, 0},
> + {TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0},
> + {TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0},
> + {TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1},
> + {TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1},
> + {TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1},
> + {TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0},
> + {TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0},
> + {TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0},
> + {TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0},
> + {TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0},
> + {TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0},
> + {TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0},
> + {TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0},
> + /* This MUST be the last entry. */
> + {TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0},
> +};
> +
--nvpublic
next prev parent reply other threads:[~2015-05-20 9:47 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-12 17:23 [PATCH v5 00/21] Tegra210 Clock Support Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 04/21] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-05-12 21:52 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 05/21] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 06/21] clk: tegra: pll: update warning msg Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 08/21] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 09/21] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
[not found] ` <1431451444-23155-11-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-18 22:35 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 11/21] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 12/21] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
[not found] ` <1431451444-23155-14-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 20:59 ` Benson Leung
[not found] ` <CANLzEkuqCB+wF65MrtWwnsgTDhw0T9Vae9C5sBALGDbPvwrr_w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-20 17:24 ` Rhyland Klein
[not found] ` <555CC357.5090105-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-20 17:26 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 14/21] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
[not found] ` <1431451444-23155-16-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 22:11 ` Benson Leung
2015-06-04 18:52 ` Stephen Boyd
2015-05-12 17:23 ` [PATCH v5 16/21] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-05-14 0:04 ` Benson Leung
2015-05-20 17:20 ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 17/21] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-05-14 0:25 ` Benson Leung
[not found] ` <CANLzEks10KmCAx4tK0oSejJ6Z+oBRS2+pcsktvStQrogCarTJQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-20 17:19 ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 18/21] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
[not found] ` <1431451444-23155-20-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-14 0:29 ` Benson Leung
2015-05-12 17:24 ` [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-13 20:36 ` Benson Leung
2015-05-14 19:37 ` Benson Leung
[not found] ` <CANLzEkvUAhXCCvtdHEfmJGONkzNu_dBHj1UUm6Et93kXV1Mz0g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-25 8:19 ` Bill Huang
[not found] ` <1431451444-23155-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-12 17:23 ` [PATCH v5 01/21] clk: tegra: Update struct tegra_clk_pll_params kerneldoc Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 01/21] FROMLIST: " Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 02/21] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 03/21] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 07/21] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 10/21] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
[not found] ` <1431451444-23155-12-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 0:01 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 13/21] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
[not found] ` <1431451444-23155-15-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 22:04 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 15/21] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
[not found] ` <1431451444-23155-17-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 22:20 ` Benson Leung
2015-05-12 17:24 ` [PATCH v5 20/21] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-14 20:23 ` Benson Leung
2015-05-20 17:17 ` Rhyland Klein
[not found] ` <1431451444-23155-22-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-20 9:47 ` Jim Lin [this message]
[not found] ` <555C582A.7050508-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-20 17:16 ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 21/21] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein
[not found] ` <1431451444-23155-23-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-14 20:02 ` Benson Leung
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