From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Xu Subject: Re: [PATCH] ARM: v7 setup function should invalidate L1 cache Date: Mon, 1 Jun 2015 11:21:40 +0100 Message-ID: <556C3234.2030805@hisilicon.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Russell King , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sh-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Andrew Lunn , Heiko Stuebner , Thierry Reding , Alexandre Courbot , Florian Fainelli , Magnus Damm , Michal Simek , bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, Sebastian Hesselbarth , Jason Cooper , Stephen Warren , yanhaifeng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, Marc Carino , Simon Horman , Gregory Fong , Gregory Clement , =?UTF-8?B?U8O2cmVuIEJyaW5rbWFubg==?= , Barry Song , Brian Norris , Christian Daudt , Sascha Hauer , Wang Long List-Id: linux-tegra@vger.kernel.org On 5/19/2015 5:12 PM, Russell King wrote: > All ARMv5 and older CPUs invalidate their caches in the early assembly > setup function, prior to enabling the MMU. This is because the L1 > cache should not contain any data relevant to the execution of the > kernel at this point; all data should have been flushed out to memory. > > This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, > these typically do not search their caches when caching is disabled (as > it needs to be when the MMU is disabled) so this change should be safe. > > ARMv7 allows there to be CPUs which search their caches while caching is > disabled, and it's permitted that the cache is uninitialised at boot; > for these, the architecture reference manual requires that an > implementation specific code sequence is used immediately after reset > to ensure that the cache is placed into a sane state. Such > functionality is definitely outside the remit of the Linux kernel, and > must be done by the SoC's firmware before _any_ CPU gets to the Linux > kernel. > > Changing the data cache clean+invalidate to a mere invalidate allows us > to get rid of a lot of platform specific hacks around this issue for > their secondary CPU bringup paths - some of which were buggy. > > Signed-off-by: Russell King > --- Hi Russell, [...] > arch/arm/mach-hisi/Makefile | 2 +- > arch/arm/mach-hisi/core.h | 1 - > arch/arm/mach-hisi/headsmp.S | 16 ---------------- > arch/arm/mach-hisi/platsmp.c | 4 ++-- [...] Sorry for the late reply. For Hisilicon: - hip01/ca9x2 - hix5hd2/dkb Tested-by: Wei Xu Thanks! Best Regards, Wei