From: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH] clk: tegra: Fixup post dividers on Tegra210
Date: Fri, 5 Feb 2016 11:36:54 -0500 [thread overview]
Message-ID: <56B4CFA6.8090301@nvidia.com> (raw)
In-Reply-To: <1454689052-25289-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 2/5/2016 11:17 AM, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Commit 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and
> _calc_dynamic_ramp_rate") changed the PLL divider computation logic to
> consistently use P-divider values from tables as real dividers rather
> than the hardware values. Unfortunately for some reason many of the
> Tegra210 clocks didn't have their tables updated (most likely an over-
> sight by me when applying the patches). This commit fixes them all up.
>
> Cc: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Cc: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-tegra210.c | 94 ++++++++++++++++++++--------------------
> 1 file changed, 47 insertions(+), 47 deletions(-)
>
Acked-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
--
nvpublic
prev parent reply other threads:[~2016-02-05 16:36 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-05 16:17 [PATCH] clk: tegra: Fixup post dividers on Tegra210 Thierry Reding
[not found] ` <1454689052-25289-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-02-05 16:36 ` Rhyland Klein [this message]
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