From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [PATCH] pinctrl: tegra: fix spelling in devicetree binding document Date: Fri, 20 Jul 2018 09:12:26 +0100 Message-ID: <5e51036b-a0b0-9cb4-4698-cf830309ef8a@nvidia.com> References: <20180720075235.18617-1-marcel@ziswiler.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180720075235.18617-1-marcel@ziswiler.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Marcel Ziswiler , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring , Mark Rutland List-Id: linux-tegra@vger.kernel.org On 20/07/18 08:52, Marcel Ziswiler wrote: > From: Marcel Ziswiler > > This fixes a spelling mistake. > > Signed-off-by: Marcel Ziswiler > > --- > > Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt > index ecb5c0d25218..f4d06bb0b55a 100644 > --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt > +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt > @@ -17,7 +17,7 @@ Tegra124 adds the following optional properties for pin configuration subnodes. > The macros for options are defined in the > include/dt-binding/pinctrl/pinctrl-tegra.h. > - nvidia,enable-input: Integer. Enable the pin's input path. > - enable :TEGRA_PIN_ENABLE0 and > + enable :TEGRA_PIN_ENABLE and > disable or output only: TEGRA_PIN_DISABLE. > - nvidia,open-drain: Integer. > enable: TEGRA_PIN_ENABLE. Thanks for fixing! Can you also fix up the one in nvidia,tegra210-pinmux.txt as well? Cheers! Jon -- nvpublic