Re: [PATCH v2 1/2] clk: tegra: divider: Add missing check for enable-bit on rate's recalculation

[Dmitry Osipenko <digetx@gmail.com>]

28.10.2019 17:27, Peter De Schrijver пишет:
> On Tue, Jul 23, 2019 at 05:52:44AM +0300, Dmitry Osipenko wrote:
>> Unset "enable" bit means that divider is in bypass mode, hence it doesn't
>> have any effect in that case. Please note that there are no known bugs
>> caused by the missing check.
>>
> 
> Technically this is not quite true, but for the purposes of CCF you can
> treat it that way. This bits defines if the value in the lower 16 bits
> of the divider register is used to configure the divider or if the
> contents of the UART DLM/DLL registers is used. So the divider isn't
> actually bypassed, it's just configured differently.
> In practice this bit is only set when the divider is non-zero when doing
> set rate. So the extra test isn't strictly needed as long as the sw
> running before the kernel also ensures the bit is only set when the
> divider is non-zero.
> 
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>

Thank you for the clarification. I hope that bootloader doesn't enable
the divider because it looks like standard 8250 driver won't be ready
for that. But serial-tegra driver seems should be good.