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From: Jon Hunter <jonathanh@nvidia.com>
To: Vishwaroop A <va@nvidia.com>,
	thierry.reding@gmail.com, skomatineni@nvidia.com,
	ldewangan@nvidia.com, broonie@kernel.org,
	linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org, kyarlagadda@nvidia.com,
	smangipudi@nvidia.com
Subject: Re: [PATCH v2 1/6] arm64: tegra: Configure QSPI clocks and add DMA
Date: Thu, 27 Feb 2025 11:13:54 +0000	[thread overview]
Message-ID: <68dcdefe-0c16-4f0a-820e-d697b862615c@nvidia.com> (raw)
In-Reply-To: <20250212144651.2433086-2-va@nvidia.com>


On 12/02/2025 14:46, Vishwaroop A wrote:
> Set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to 99.99 MHz using
> PLLC as the parent clock. These frequencies allow Quad IO DT
> reads up to 99.99 MHz, which is the fastest that can be
> achieved considering various PLL and clock divider constraints.
> 
> Populate the DMA and IOMMU properties for the Tegra234 QSPI devices to
> enable DMA support.
> 
> Signed-off-by: Vishwaroop A <va@nvidia.com>
> ---
>   arch/arm64/boot/dts/nvidia/tegra234.dtsi | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index 2601b43b2d8c..0ac2d3aba930 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -2948,6 +2948,13 @@
>   				 <&bpmp TEGRA234_CLK_QSPI0_PM>;
>   			clock-names = "qspi", "qspi_out";
>   			resets = <&bpmp TEGRA234_RESET_QSPI0>;
> +			assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
> +					  <&bpmp TEGRA234_CLK_QSPI0_PM>;
> +			assigned-clock-rates = <199999999 99999999>;
> +			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
> +			dma-names = "rx", "tx";
> +			dma-coherent;
> +			iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
>   			status = "disabled";
>   		};
>   
> @@ -3031,6 +3038,13 @@
>   				 <&bpmp TEGRA234_CLK_QSPI1_PM>;
>   			clock-names = "qspi", "qspi_out";
>   			resets = <&bpmp TEGRA234_RESET_QSPI1>;
> +			assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
> +					  <&bpmp TEGRA234_CLK_QSPI1_PM>;
> +			assigned-clock-rates = <199999999 99999999>;
> +			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
> +			dma-names = "rx", "tx";
> +			dma-coherent;
> +			iommus = <&smmu_niso1 TEGRA234_SID_QSPI1>;
>   			status = "disabled";
>   		};
>   


Make sure you CC the DT mailing list on this.

With this change I am seeing the following warnings ...

arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dtb: spi@3270000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected)
	from schema $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
   DTC [C] arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0008.dtb
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0008.dtb: spi@3270000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected)
	from schema $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
   DTC [C] arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dtb
arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dtb: spi@3270000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected)
	from schema $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
   DTC [C] arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dtb
arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dtb: spi@3270000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected)
	from schema $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
   DTC [C] arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dtb
arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dtb: spi@3270000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected)
	from schema $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#

Jon

-- 
nvpublic


  parent reply	other threads:[~2025-02-27 11:14 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-03  6:04 [PATCH 0/6] Configure Clocks, Add Native Dma support Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 1/6] arm64: tegra: Configure QSPI clocks and add DMA Vishwaroop A
2025-01-09 10:40   ` Thierry Reding
2025-02-12 14:39     ` Vishwaroop A
2025-03-07 13:28       ` Jon Hunter
2025-02-12 14:46     ` [PATCH v2 0/6] Configure Clocks, Add Native Dma support Vishwaroop A
2025-02-12 14:46       ` [PATCH v2 1/6] arm64: tegra: Configure QSPI clocks and add DMA Vishwaroop A
2025-02-27 10:39         ` Thierry Reding
2025-02-27 11:13         ` Jon Hunter [this message]
2025-02-12 14:46       ` [PATCH v2 2/6] spi: tegra210-quad: Update dummy sequence configuration Vishwaroop A
2025-02-27 10:42         ` Thierry Reding
2025-02-12 14:46       ` [PATCH v2 3/6] spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfers Vishwaroop A
2025-02-27 10:45         ` Thierry Reding
2025-02-12 14:46       ` [PATCH v2 4/6] spi: tegra210-quad: remove redundant error handling code Vishwaroop A
2025-02-27 10:45         ` Thierry Reding
2025-02-12 14:46       ` [PATCH v2 5/6] spi: tegra210-quad: modify chip select (CS) deactivation Vishwaroop A
2025-02-27 10:46         ` Thierry Reding
2025-02-12 14:46       ` [PATCH v2 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A
2025-02-27 11:14         ` Thierry Reding
2025-02-27 11:17         ` Jon Hunter
2025-02-12 22:08       ` [PATCH v2 0/6] Configure Clocks, Add Native Dma support Rob Herring (Arm)
2025-02-27 11:09       ` Jon Hunter
2025-01-03  6:04 ` [PATCH V1 2/6] spi: tegra210-quad: Update dummy sequence configuration Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 3/6] spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfers Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 4/6] spi: tegra210-quad: remove redundant error handling code Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 5/6] spi: tegra210-quad: modify chip select (CS) deactivation Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A
2025-01-03 14:21   ` kernel test robot
2025-01-03 23:16   ` kernel test robot
2025-01-06 13:04   ` Mark Brown

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