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From: "Dan Williams (nvidia)" <djbw@kernel.org>
To: Srirangan Madhavan <smadhavan@nvidia.com>,
	 Alison Schofield <alison.schofield@intel.com>,
	 Bjorn Helgaas <bhelgaas@google.com>,
	 Dan Williams <djbw@kernel.org>,
	 Dave Jiang <dave.jiang@intel.com>,
	 Davidlohr Bueso <dave@stgolabs.net>,
	 Ira Weiny <ira.weiny@intel.com>,
	 Jonathan Cameron <jic23@kernel.org>,
	 Vishal Verma <vishal.l.verma@intel.com>,
	 linux-cxl@vger.kernel.org,  linux-pci@vger.kernel.org,
	 linux-kernel@vger.kernel.org
Cc: vsethi@nvidia.com,  alwilliamson@nvidia.com,
	 Dan Williams <danwilliams@nvidia.com>,
	 Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	 Vishal Aslot <vaslot@nvidia.com>,
	 Manish Honap <mhonap@nvidia.com>,  Jiandi An <jan@nvidia.com>,
	 Richard Cheng <icheng@nvidia.com>,
	 linux-tegra@vger.kernel.org,
	 Srirangan Madhavan <smadhavan@nvidia.com>
Subject: Re: [PATCH v7 02/11] cxl: Cache decoder settings on PCI devices
Date: Tue, 23 Jun 2026 16:13:35 -0700	[thread overview]
Message-ID: <6a3b131f453df_3c9f100db@djbw-dev.notmuch> (raw)
In-Reply-To: <20260623032453.3404772-3-smadhavan@nvidia.com>

Srirangan Madhavan wrote:
> Cache CXL core's HDM decoder settings in pci_dev->hdm as decoders are
> enumerated, committed, or reset. PCI reset paths can use this snapshot to
> restore HDM programming without walking CXL topology during reset recovery.
> 
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> ---
>  drivers/cxl/core/hdm.c | 81 +++++++++++++++++++++++++++++++++++++++++-
>  include/cxl/cxl.h      | 12 +++++++
>  include/linux/pci.h    |  6 ++++
>  3 files changed, 98 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index fa978c297546..83cda63f76a5 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -84,6 +84,76 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
>  		cxlhdm->iw_cap_mask |= BIT(16);
>  }
>  
> +static void clear_hdm_info(void *data)
> +{
> +	struct pci_dev *pdev = data;
> +
> +	WRITE_ONCE(pdev->hdm, NULL);
> +}
> +
> +static int devm_cxl_pci_setup_hdm_info(struct cxl_hdm *cxlhdm)
> +{
> +	struct cxl_port *port = cxlhdm->port;
> +	struct cxl_hdm_info *info;
> +	struct pci_dev *pdev;
> +	struct device *uport;
> +
> +	if (is_cxl_endpoint(port)) {
> +		struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
> +
> +		uport = cxlmd->dev.parent;
> +	} else {
> +		uport = port->uport_dev;
> +	}
> +
> +	if (!dev_is_pci(uport))
> +		return 0;
> +
> +	pdev = to_pci_dev(uport);
> +	info = devm_kzalloc(&pdev->dev,
> +			    struct_size(info, settings, cxlhdm->decoder_count),
> +			    GFP_KERNEL);
> +	if (!info)
> +		return -ENOMEM;
> +
> +	info->decoder_count = cxlhdm->decoder_count;
> +	WRITE_ONCE(pdev->hdm, info);
> +
> +	return devm_add_action_or_reset(&pdev->dev, clear_hdm_info, pdev);

The CXL core can update the PCI cached HDM settings under the device
lock, but it should not be doing its own allocation. It also should not
clear the cached settings on shutdown. That would defeat the purpose of
having the HDM settings available while the device is disabled.

  reply	other threads:[~2026-06-23 23:13 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-23  3:24 [PATCH v7 00/11] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-06-23  3:24 ` [PATCH v7 01/11] cxl: Split decoder programming into a reusable helper Srirangan Madhavan
2026-06-23  3:24 ` [PATCH v7 02/11] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-06-23 23:13   ` Dan Williams (nvidia) [this message]
2026-06-23  3:24 ` [PATCH v7 03/11] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-06-24  2:15   ` Dan Williams (nvidia)
2026-06-23  3:24 ` [PATCH v7 04/11] PCI: Export pci_dev_save_and_disable() and pci_dev_restore() Srirangan Madhavan
2026-06-24  2:17   ` Dan Williams (nvidia)
2026-06-23  3:24 ` [PATCH v7 05/11] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-06-23  3:24 ` [PATCH v7 06/11] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-06-23  3:24 ` [PATCH v7 07/11] PCI/cxl: Discover the CXL reset scope Srirangan Madhavan
2026-06-23  3:24 ` [PATCH v7 08/11] cxl: Coordinate sibling functions for CXL reset Srirangan Madhavan
2026-06-23 23:00   ` Dan Williams (nvidia)
2026-06-23  3:24 ` [PATCH v7 09/11] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-06-23  3:24 ` [PATCH v7 10/11] PCI/cxl: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-06-23  3:24 ` [PATCH v7 11/11] Documentation/ABI: Document CXL Reset " Srirangan Madhavan

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