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Wysocki" CC: , , , , , , , , , , , Sumit Gupta References: <20231006153612.5851-1-sumitg@nvidia.com> <20231006153612.5851-3-sumitg@nvidia.com> From: Sumit Gupta In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4D:EE_|DS7PR12MB6117:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bbec335-732a-4646-e773-08dbc8ed4379 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fWLMvzMxWYsj5dXdo5moNAYsQFnkwT0IZx15ZIVffjI30bgxZH9vb5bKGFOuCVUMCo0wYKc5XyKt7iVEQAyfeAW+o40jTJSg24cy+v2AasqlbyoMJW0ffA8t6gXmMFgbtaO5Vn2jy0ppC+6SH2DXI192ZLkb6ZjiIKFyInVw2FQlwRH0ihLwkNjWGFolfuzTmNnuHA75RkKq9wGkupG8d10nNCOYeWVV4ECjjSh/8X8u9BWgrk5CJ031YqlVOkQBRl5roZmZF9kskA6wKaWPGKfb8ohLwUxpspuGKJP8+m4O5Q+2YRDh5gnRPGJ3+/6nuqBgBQS5DCV7xjITZfNUj7Ob7PWir1fpQ1VLIkjmbDQqYtkeyyX7VBWnp3pdCkqWpLHkkE7hHTjvFaqkqHpUKc50ZbBlHh+CWFXYtwhcZFPGMNWzqdnOxQHrxBL4d5WKX1sfLBM1gdlaszkjTTgmpdJ3oaH4uPpNwI/GtYMnPbf8xRrZQQZhTn1X0t0j7DcCBsUhmd04GwDkqRKi/AGMajS11iSZIsXWoyfRTkiZeCp9DNrkeEHjXqH+pcfhMIvFcfqgDqMKyxLfWLIYgbziouBjfTo5dS5iU5YuAQ+osNAaY1EhxEx+hGeUWyRQa/ZHJg8gjNGYTVrXPhV9LYXfD6JZKv46EmjxPVsz9sGaM6AQHTJHg+H0WPzcC7NSF7mF9KCehe3Ly/rE4pO6uJV4g+ftG2AB0ED3zEUXFLlG+Cy34M7ueB+kXR7O2W8HEkK53WbBzOnu1nwyZquOx8JeS7nREHOkNi0klXGQim3xvLu8l8ybEShsf3MBbHNtu9/I X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(346002)(39860400002)(376002)(230922051799003)(82310400011)(64100799003)(186009)(1800799009)(451199024)(36840700001)(40470700004)(46966006)(83380400001)(107886003)(6666004)(16526019)(26005)(82740400003)(2616005)(7636003)(356005)(966005)(70586007)(41300700001)(47076005)(31686004)(336012)(53546011)(426003)(478600001)(316002)(16576012)(70206006)(6916009)(54906003)(36860700001)(5660300002)(8936002)(86362001)(4326008)(31696002)(40480700001)(36756003)(8676002)(40460700003)(2906002)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 17:29:16.6361 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bbec335-732a-4646-e773-08dbc8ed4379 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6117 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On 06/10/23 21:22, Rafael J. Wysocki wrote: > External email: Use caution opening links or attachments > > > On Fri, Oct 6, 2023 at 5:36 PM Sumit Gupta wrote: >> >> From: Srikar Srimath Tirumala >> >> Current implementation of processor_thermal performs software throttling >> in fixed steps of "20%" which can be too coarse for some platforms. >> We observed some performance gain after reducing the throttle percentage. >> Change the CPUFREQ thermal reduction percentage and maximum thermal steps >> to be configurable. Also, update the default values of both for Nvidia >> Tegra241 (Grace) SoC. The thermal reduction percentage is reduced to "5%" >> and accordingly the maximum number of thermal steps are increased as they >> are derived from the reduction percentage. >> >> Signed-off-by: Srikar Srimath Tirumala >> Signed-off-by: Sumit Gupta >> --- >> drivers/acpi/processor_thermal.c | 43 +++++++++++++++++++++++++++++--- >> 1 file changed, 40 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/acpi/processor_thermal.c b/drivers/acpi/processor_thermal.c >> index b7c6287eccca..677ba8bc3fbc 100644 >> --- a/drivers/acpi/processor_thermal.c >> +++ b/drivers/acpi/processor_thermal.c >> @@ -26,7 +26,16 @@ >> */ >> >> #define CPUFREQ_THERMAL_MIN_STEP 0 >> -#define CPUFREQ_THERMAL_MAX_STEP 3 >> + >> +static int cpufreq_thermal_max_step __read_mostly = 3; >> + >> +/* >> + * Minimum throttle percentage for processor_thermal cooling device. >> + * The processor_thermal driver uses it to calculate the percentage amount by >> + * which cpu frequency must be reduced for each cooling state. This is also used >> + * to calculate the maximum number of throttling steps or cooling states. >> + */ >> +static int cpufreq_thermal_pctg __read_mostly = 20; >> >> static DEFINE_PER_CPU(unsigned int, cpufreq_thermal_reduction_pctg); >> >> @@ -71,7 +80,7 @@ static int cpufreq_get_max_state(unsigned int cpu) >> if (!cpu_has_cpufreq(cpu)) >> return 0; >> >> - return CPUFREQ_THERMAL_MAX_STEP; >> + return cpufreq_thermal_max_step; >> } >> >> static int cpufreq_get_cur_state(unsigned int cpu) >> @@ -113,7 +122,8 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state) >> if (!policy) >> return -EINVAL; >> >> - max_freq = (policy->cpuinfo.max_freq * (100 - reduction_pctg(i) * 20)) / 100; >> + max_freq = (policy->cpuinfo.max_freq * >> + (100 - reduction_pctg(i) * cpufreq_thermal_pctg)) / 100; >> >> cpufreq_cpu_put(policy); >> >> @@ -126,10 +136,37 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state) >> return 0; >> } >> >> +#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY >> +#define SMCCC_SOC_ID_T241 0x036b0241 >> + >> +static void acpi_thermal_cpufreq_config_nvidia(void) >> +{ >> + s32 soc_id = arm_smccc_get_soc_id_version(); >> + >> + /* Check JEP106 code for NVIDIA Tegra241 chip (036b:0241) */ >> + if (soc_id < 0 || soc_id != SMCCC_SOC_ID_T241) >> + return; >> + >> + /* Reduce the CPUFREQ Thermal reduction percentage to 5% */ >> + cpufreq_thermal_pctg = 5; >> + >> + /* >> + * Derive the MAX_STEP from minimum throttle percentage so that the reduction >> + * percentage doesn't end up becoming negative. Also, cap the MAX_STEP so that >> + * the CPU performance doesn't become 0. >> + */ >> + cpufreq_thermal_max_step = (100 / cpufreq_thermal_pctg) - 1; >> +} > > Looks better now, but one more thing: This is introducing an > ARM-specific piece of code into an otherwise generic file and there is > drivers/acpi/arm64/ for ARM-specific code, so I would very much prefer > this piece of code to go there. > > Of course, it won't be able to modify the static variables directly > then, but what if instead it defines functions to return the > appropriate values? > > The variables in question could be initialized with the help of those > functions then. > Hi Rafael, Thank you for the review! Have done the suggested change and sent v4[1]. Please suggest if it looks fine now (or) needs any further change. [1] https://lore.kernel.org/lkml/20231009171839.12267-1-sumitg@nvidia.com/ Best Regards, Sumit Gupta >> +#else >> +static inline void acpi_thermal_cpufreq_config_nvidia(void) {} >> +#endif >> + >> void acpi_thermal_cpufreq_init(struct cpufreq_policy *policy) >> { >> unsigned int cpu; >> >> + acpi_thermal_cpufreq_config_nvidia(); >> + >> for_each_cpu(cpu, policy->related_cpus) { >> struct acpi_processor *pr = per_cpu(processors, cpu); >> int ret; >> -- >> 2.17.1 >>