From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19A772940D; Thu, 9 Oct 2025 14:30:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760020260; cv=none; b=bsnRZhd4TtWUX7WLp9qUJsvY+MCUPQWeKqYvnh5aHVWJEZb6XBcfxU5PbP8v/m/dODlJr80m1Z8e77tzhrOy3ipzhfBFfNi2p9w2V4liFnb/Yh2SHmIo+jUpMSC8br5o2NwMtbconxQ0njdPCiROpMsDjbdf4H9ymFc3g2F2Wao= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760020260; c=relaxed/simple; bh=by7B82JNtuWconqfgRH2IEjHTUBvVgCQlC/h4bYSBsA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=AqaCh0p0+lnFP+aOQGRKIkGA7yLnP97XNIgPChM5vlfcawjeyCx4WE7fTokxYXFASrxsWa2sbv4Rx+xSWk0CXzcUk5L2BIRMFiTx7nH+ZOxsDIQLuO+nNy/lQPjVXei0FvTKbiSk0g//E+tiSTWzVCKDfMCpmdqRxw4u8XhQbxM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dY5mvCf9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dY5mvCf9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9E55DC4CEE7; Thu, 9 Oct 2025 14:30:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760020259; bh=by7B82JNtuWconqfgRH2IEjHTUBvVgCQlC/h4bYSBsA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=dY5mvCf9PB0wbd7hHCmC15O4xQ7B/3eWJp66y7FLCawXvUAS8z8Ga4eByBfPCZnGs SMRV9o1J0xua7LV3sR0NvPuaXlqnURAuxQnVfDTlqmmNorn25JD0oOSnD3DjrMD505 8iSp5LFsUqRRDTs3Fc380LWy89ZfKzNGGJeMWOwC89bwX2YotWPNw8x/2Gu1Mp2hAa 32vXen4iDp44KhuWGJvP2a7sdVLouPubDhi7px+bbtlS1+l3BuBTfHXhfCQ95ixhKB f3KBTpvL4E0xT/nfqj/c7aJdytyvRWvMSUeKJCgayHSr7UTnDAU8WQJkybNzi6L6nI QSLDTzHSRG6GQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v6rfV-0000000CeiY-1hQI; Thu, 09 Oct 2025 14:30:57 +0000 Date: Thu, 09 Oct 2025 15:30:56 +0100 Message-ID: <86qzvcxi3j.wl-maz@kernel.org> From: Marc Zyngier To: Thierry Reding Cc: Thomas Gleixner , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: IRQ thread timeouts and affinity In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: thierry.reding@gmail.com, tglx@linutronix.de, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Hi Thierry, On Thu, 09 Oct 2025 12:38:55 +0100, Thierry Reding wrote: > > Which brings me to the actual question: what is the right way to solve > this? I had, maybe naively, assumed that the default CPU affinity, which > includes all available CPUs, would be sufficient to have interrupts > balanced across all of those CPUs, but that doesn't appear to be the > case. At least not with the GIC (v3) driver which selects one CPU (CPU 0 > in this particular case) from the affinity mask to set the "effective > affinity", which then dictates where IRQs are handled and where the > corresponding IRQ thread function is run. There's a (GIC-specific) answer to that, and that's the "1 of N" distribution model. The problem is that it is a massive headache (it completely breaks with per-CPU context). We could try and hack this in somehow, but defining a reasonable API is complicated. The set of CPUs receiving 1:N interrupts is a *global* set, which means you cannot have one interrupt targeting CPUs 0-1, and another targeting CPUs 2-3. You can only have a single set for all 1:N interrupts. How would you define such a set in a platform agnostic manner so that a random driver could use this? I definitely don't want to have a GIC-specific API. Overall, there is quite a lot of work to be done in this space: the machine I'm typing this from doesn't have affinity control *at all*. Any interrupt can target any CPU, and if Linux doesn't expect that, tough. Don't even think of managed interrupts on that sort of systems... M. -- Without deviation from the norm, progress is not possible.