From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62DABC6FA86 for ; Tue, 13 Sep 2022 07:15:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230523AbiIMHPd (ORCPT ); Tue, 13 Sep 2022 03:15:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230416AbiIMHPc (ORCPT ); Tue, 13 Sep 2022 03:15:32 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [IPv6:2001:67c:2178:6::1c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99AB2286D9; Tue, 13 Sep 2022 00:15:30 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id A70FA34880; Tue, 13 Sep 2022 07:15:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1663053329; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Asp3tq6eKpLmJQrxdQF0k5WefKNzKndJj+3xTCza4Jc=; b=AOEl/V1myWlE6Y4/RfD9xo9TsT+4dYd391jrdMVYaPWb7xQhbZK0wxbBmj/dQOhOMGPG4Z vDEyLauwUfJg4AWfzeAuwgrviT5/KVrRn82wTjD+wfk5QnYqCkdqXctj70ArVIfqu5gLsg fHWgacGmQTxGgQgnCP+z4zTJaQp5FqM= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1663053329; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Asp3tq6eKpLmJQrxdQF0k5WefKNzKndJj+3xTCza4Jc=; b=dOOJHHnZbmeqMOfv44zy0dnRHX/qUwKP06n4R+5ZXL7TdHgb3BbJdWI/HabGuSM0T+xzvu mEhfLOrtCy9m/0Bw== Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 7ABF513AB5; Tue, 13 Sep 2022 07:15:29 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id Q9w/HREuIGOBegAAMHmgww (envelope-from ); Tue, 13 Sep 2022 07:15:29 +0000 Date: Tue, 13 Sep 2022 09:15:28 +0200 Message-ID: <874jxbhhin.wl-tiwai@suse.de> From: Takashi Iwai To: Mohan Kumar Cc: , , , , , , Subject: Re: [v2] ALSA: hda: Fix Nvidia dp infoframe In-Reply-To: <20220913065818.13015-1-mkumard@nvidia.com> References: <20220913065818.13015-1-mkumard@nvidia.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) Emacs/27.2 Mule/6.0 MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On Tue, 13 Sep 2022 08:58:18 +0200, Mohan Kumar wrote: > > Nvidia HDA HW expects infoframe data bytes order same for both > HDMI and DP i.e infoframe data starts from 5th bytes offset. As > dp infoframe structure has 4th byte as valid infoframe data, use > hdmi infoframe structure for nvidia dp infoframe to match HW behvaior. > > Signed-off-by: Mohan Kumar Aha, so this affects on all Nvidia devices, not only on Tegra, but also on PC? Then we should put cc-to-stable definitely. (No need to resend, I can put it locally.) Takashi > --- > sound/pci/hda/patch_hdmi.c | 23 +++++++++++++++++++---- > 1 file changed, 19 insertions(+), 4 deletions(-) > > diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c > index 6c209cd26c0c..9127dd1b1a9c 100644 > --- a/sound/pci/hda/patch_hdmi.c > +++ b/sound/pci/hda/patch_hdmi.c > @@ -170,6 +170,8 @@ struct hdmi_spec { > bool dyn_pcm_no_legacy; > /* hdmi interrupt trigger control flag for Nvidia codec */ > bool hdmi_intr_trig_ctrl; > + bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */ > + > bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ > /* > * Non-generic VIA/NVIDIA specific > @@ -679,15 +681,24 @@ static void hdmi_pin_setup_infoframe(struct hda_codec *codec, > int ca, int active_channels, > int conn_type) > { > + struct hdmi_spec *spec = codec->spec; > union audio_infoframe ai; > > memset(&ai, 0, sizeof(ai)); > - if (conn_type == 0) { /* HDMI */ > + if ((conn_type == 0) || /* HDMI */ > + /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */ > + (conn_type == 1 && spec->nv_dp_workaround)) { > struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; > > - hdmi_ai->type = 0x84; > - hdmi_ai->ver = 0x01; > - hdmi_ai->len = 0x0a; > + if (conn_type == 0) { /* HDMI */ > + hdmi_ai->type = 0x84; > + hdmi_ai->ver = 0x01; > + hdmi_ai->len = 0x0a; > + } else {/* Nvidia DP */ > + hdmi_ai->type = 0x84; > + hdmi_ai->ver = 0x1b; > + hdmi_ai->len = 0x11 << 2; > + } > hdmi_ai->CC02_CT47 = active_channels - 1; > hdmi_ai->CA = ca; > hdmi_checksum_audio_infoframe(hdmi_ai); > @@ -3617,6 +3628,7 @@ static int patch_nvhdmi_2ch(struct hda_codec *codec) > spec->pcm_playback.rates = SUPPORTED_RATES; > spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; > spec->pcm_playback.formats = SUPPORTED_FORMATS; > + spec->nv_dp_workaround = true; > return 0; > } > > @@ -3756,6 +3768,7 @@ static int patch_nvhdmi(struct hda_codec *codec) > spec->chmap.ops.chmap_cea_alloc_validate_get_type = > nvhdmi_chmap_cea_alloc_validate_get_type; > spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; > + spec->nv_dp_workaround = true; > > codec->link_down_at_suspend = 1; > > @@ -3779,6 +3792,7 @@ static int patch_nvhdmi_legacy(struct hda_codec *codec) > spec->chmap.ops.chmap_cea_alloc_validate_get_type = > nvhdmi_chmap_cea_alloc_validate_get_type; > spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; > + spec->nv_dp_workaround = true; > > codec->link_down_at_suspend = 1; > > @@ -3992,6 +4006,7 @@ static int tegra_hdmi_init(struct hda_codec *codec) > spec->chmap.ops.chmap_cea_alloc_validate_get_type = > nvhdmi_chmap_cea_alloc_validate_get_type; > spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; > + spec->nv_dp_workaround = true; > > return 0; > } > -- > 2.17.1 >