From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [PATCH net-next 3/3] net: stmmac: Introducing support for Page Pool Date: Tue, 23 Jul 2019 13:09:00 +0100 Message-ID: <8756d681-e167-fe4a-c6f0-47ae2dcbb100@nvidia.com> References: <1b254bb7fc6044c5e6e2fdd9e00088d1d13a808b.1562149883.git.joabreu@synopsys.com> <29dcc161-f7c8-026e-c3cc-5adb04df128c@nvidia.com> <20190722101830.GA24948@apalos> <11557fe0-0cba-cb49-0fb6-ad24792d4a53@nvidia.com> <6c769226-bdd9-6fe0-b96b-5a0d800fed24@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <6c769226-bdd9-6fe0-b96b-5a0d800fed24@arm.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Robin Murphy , Jose Abreu , Lars Persson , Ilias Apalodimas Cc: Joao Pinto , Alexandre Torgue , Maxime Ripard , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , Chen-Yu Tsai , Maxime Coquelin , linux-tegra , Giuseppe Cavallaro , "David S . Miller" , "linux-arm-kernel@lists.infradead.org" List-Id: linux-tegra@vger.kernel.org On 23/07/2019 11:29, Robin Murphy wrote: > On 23/07/2019 11:07, Jose Abreu wrote: >> From: Jon Hunter >> Date: Jul/23/2019, 11:01:24 (UTC+00:00) >> >>> This appears to be a winner and by disabling the SMMU for the ethernet >>> controller and reverting commit 954a03be033c7cef80ddc232e7cbdb17df73566= 3 >>> this worked! So yes appears to be related to the SMMU being enabled. We >>> had to enable the SMMU for ethernet recently due to commit >>> 954a03be033c7cef80ddc232e7cbdb17df735663. >> >> Finally :) >> >> However, from "git show 954a03be033c7cef80ddc232e7cbdb17df735663": >> >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 There are few reasons = to allow unmatched stream bypass, and >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 even fewer good ones.= =C2=A0 If saying YES here breaks your board >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 you should work on fix= ing your board. >> >> So, how can we fix this ? Is your ethernet DT node marked as >> "dma-coherent;" ? >=20 > The first thing to try would be booting the failing setup with > "iommu.passthrough=3D1" (or using CONFIG_IOMMU_DEFAULT_PASSTHROUGH) - if > that makes things seem OK, then the problem is likely related to address > translation; if not, then it's probably time to start looking at nasties > like coherency and ordering, although in principle I wouldn't expect the > SMMU to have too much impact there. Setting "iommu.passthrough=3D1" works for me. However, I am not sure where to go from here, so any ideas you have would be great. > Do you know if the SMMU interrupts are working correctly? If not, it's > possible that an incorrect address or mapping direction could lead to > the DMA transaction just being silently terminated without any fault > indication, which generally presents as inexplicable weirdness (I've > certainly seen that on another platform with the mix of an unsupported > interrupt controller and an 'imperfect' ethernet driver). If I simply remove the iommu node for the ethernet controller, then I see lots of ... [ 6.296121] arm-smmu 12000000.iommu: Unexpected global fault, this could= be serious [ 6.296125] arm-smmu 12000000.iommu: GFSR 0x00000002, GFSYNR0 0x= 00000000, GFSYNR1 0x00000014, GFSYNR2 0x00000000 So I assume that this is triggering the SMMU interrupt correctly.=20 > Just to confirm, has the original patch been tested with > CONFIG_DMA_API_DEBUG to rule out any high-level mishaps? Yes one of the first things we tried but did not bare any fruit. Cheers Jon --=20 nvpublic