Re: [RFC 04/10] memory: Add Tegra124 memory controller support

[Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]

Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> writes:

> diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h
> new file mode 100644
> index 000000000000..6b1617ce022f
> --- /dev/null
> +++ b/include/dt-bindings/memory/tegra124-mc.h
> @@ -0,0 +1,30 @@
> +#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
> +#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
> +
> +#define TEGRA_SWGROUP_DC       0
> +#define TEGRA_SWGROUP_DCB      1
> +#define TEGRA_SWGROUP_AFI      2
> +#define TEGRA_SWGROUP_AVPC     3
> +#define TEGRA_SWGROUP_HDA      4
> +#define TEGRA_SWGROUP_HC       5
> +#define TEGRA_SWGROUP_MSENC    6
> +#define TEGRA_SWGROUP_PPCS     7
> +#define TEGRA_SWGROUP_SATA     8
> +#define TEGRA_SWGROUP_VDE      9
> +#define TEGRA_SWGROUP_MPCORELP 10
> +#define TEGRA_SWGROUP_MPCORE   11
> +#define TEGRA_SWGROUP_ISP2     12
> +#define TEGRA_SWGROUP_XUSB_HOST        13
> +#define TEGRA_SWGROUP_XUSB_DEV 14
> +#define TEGRA_SWGROUP_ISP2B    15
> +#define TEGRA_SWGROUP_TSEC     16
> +#define TEGRA_SWGROUP_A9AVP    17
> +#define TEGRA_SWGROUP_GPU      18
> +#define TEGRA_SWGROUP_SDMMC1A  19
> +#define TEGRA_SWGROUP_SDMMC2A  20
> +#define TEGRA_SWGROUP_SDMMC3A  21
> +#define TEGRA_SWGROUP_SDMMC4A  22
> +#define TEGRA_SWGROUP_VIC      23
> +#define TEGRA_SWGROUP_VI       24
> +
> +#endif

In the SMMUv8 patch series, I have assigned unique IDs for all those
HWAs among Tegra SoC generations so that DT can provide which HWAs are
attached to that SoC. The SMMUv8 driver would be unified among Tegra
SoCs, then.