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[109.252.138.136]) by smtp.googlemail.com with ESMTPSA id n15sm3344584ljh.36.2022.02.01.05.06.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Feb 2022 05:06:18 -0800 (PST) Message-ID: <9900cecc-8e00-5b34-a8b2-95d8e1c1ad77@gmail.com> Date: Tue, 1 Feb 2022 16:06:17 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v17 2/4] dmaengine: tegra: Add tegra gpcdma driver Content-Language: en-US To: Akhil R Cc: "devicetree@vger.kernel.org" , "dmaengine@vger.kernel.org" , Jonathan Hunter , Krishna Yarlagadda , Laxman Dewangan , "linux-kernel@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "p.zabel@pengutronix.de" , Rajesh Gumasta , "robh+dt@kernel.org" , "thierry.reding@gmail.com" , "vkoul@kernel.org" , Pavan Kunapuli References: <1643474453-32619-1-git-send-email-akhilrajeev@nvidia.com> <1643474453-32619-3-git-send-email-akhilrajeev@nvidia.com> <08f6571e-af75-b6b3-443e-e86e3bdb365b@gmail.com> <20220131094205.73f5f8c3@dimatab> <8abf2da8-9a11-8f16-b495-d8ef2d00ab51@gmail.com> <6dfdfd02-bfc3-1626-f819-7ddcc8bf9c1c@gmail.com> From: Dmitry Osipenko In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org 01.02.2022 15:05, Akhil R пишет: >> 31.01.2022 18:38, Akhil R пишет: >>> Does the below method look good? bytes_xfer is updated on every ISR and in >>> tx_status(), the wcount is read to calculate the intermittent value. If the >> transfer >>> get complete in between, use wcount as 0 to add sg_req.len to bytes_xfer >>> >>> static int tegra_dma_get_residual(struct tegra_dma_channel *tdc) >>> { >>> unsigned long wcount = 0, status; >>> unsigned int bytes_xfer, residual; >>> struct tegra_dma_desc *dma_desc = tdc->dma_desc; >>> struct tegra_dma_sg_req *sg_req = dma_desc->sg_req; >>> >>> /* >>> * Do not read from CHAN_XFER_COUNT if EOC bit is set >>> * as the transfer would have already completed and >>> * the register could have updated for next transfer >>> * in case of cyclic transfers. >>> */ >>> status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); >>> if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC)) >>> wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT); >> >> You can't read WCOUNT after the STATUS without racing with the STATUS >> updates made by h/w. You should read the WCOUNT first and only then >> check the STATUS. >> >> You should also check whether T20 tegra_dma_sg_bytes_xferred() >> workarounds apply to newer h/w. I see that the h/w base hasn't changed >> much since T20. > The calculation in T20 driver is not applicable here. The register shows the > actual number of words remaining to be transferred as far as I understand. If downstream kernel DMA driver doesn't have any special quirks, then likely that they are indeed unneeded.